International Business Machines Corporation

Jose A Olive

Mark G Noll

Roberto V Perez

Terence J Lohman

James Peter Ward

Peter Juergen Klim

Grant L Clarke, Jr

Margaret E Claffey-Cohen

Rick L Horne

A method for color conversion includes calculating distances between color coordinates in a conversion palette and a color coordinate for a pixel and assigning the pixel a color coordinate of the closest color coordinates in the conversion palette. The color coordinates in the conversion palette include a first point and a second point in an RGB color cube on a neutral axis of said RGB color cube and on opposite surfaces of a first sphere, a third point and a fourth point on the neutral axis and on opposite surfaces of a second sphere and on the neutral axis, and a plurality of other points distributed over a surface of the first sphere and around the neutral axis, where a volume of the second sphere is twice the volume of the first sphere, and a center of the first and second spheres is a center of the RGB color cube.

RGB color conversion palettes

A method and apparatus for bypassing a boundary-scan cell during functional operation of an electronic component provides a component output signal (such as a data signal) to a boundary-scan bypass circuit during normal functional operation of the electronic component. The component output signal is multiplexed in the bypass circuit with the test result signal that occurs during boundary-scan testing. During functional operation of the electronic component, the component output signal is selected and provided to an output latch that is clocked by a transition of the clock signal of the electronic component. By bypassing the component output signal around the boundary-scan cell during normal operation, the traversing of the multiplexer by the component output signal after the transition of the clock signal of the component is avoided, thereby reducing off-chip delay.

Boundary-scan bypass circuit for integrated circuit electronic component

A timeout mechanism for a computer system is provided, comprising a clocked linear feedback shift register and a programmable comparing mechanism. The linear feedback shift register comprises a series of latches serially connected to each other, and is responsive to a received interrupt signal to (i) incrementally count sequentially in the presence of the interrupt signal to provide a distinct binary vector array at the outputs of the latches for each count in the sequence and (ii) reset to a particular binary vector array in the absence of the interrupt signal. The comparing mechanism outputs a timeout command in response to the linear feedback shift register reaching a predetermined count and outputting a corresponding predetermined binary vector array at the output of the latches. The timeout mechanism uses a minimal amount of combinatorial logic, while permitting the issuance of a timeout command after the detection of an interrupt signal after any multiple of clock cycles.

Programmable linear feedback shift register timeout mechanism

A computer system that has a processor that services interrupts in response to receipt of a signal at the interrupt request has a first device and a second device coupled to the processor. The first device is capable of transmitting a first interrupt request signal that includes an edge transition. The second device is capable of transmitting a second interrupt request signal that comprises a level assertion. An interrupt handler is coupled to the processor and the first and second devices, the interrupt handler receiving the first and second interrupt request signals as inputs and providing the first and second interrupt request signals as outputs to the processor in a sequence according to a predetermined criteria, the first and second interrupt request signals having identical priority.

Computer system and method with integrated level and edge interrupt

A personal computer has two possible memory sizes differing by the maximum number SIMMs that can be installed. Each SIMM stores presence detect bits indicating the size and speed of the SIMM. An I/O controller includes a memory detect port which is used to read the presence detect bits from the SIMMs. The controller further includes a logic circuit that is set in accordance with the memory size to selectively control driving the presence detect bits or empty socket bits onto a data bus.

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Miami, FL, United States of America

Jose A Olive