Cadence Design Systems, Inc.

Jose A Martinez

Regis R Colwell

David Allan White

Arnold Ginetti

Wangyang Zhang

Elias Lee Fallon

Jeffrey Markham

Chung-Do Yang

Steven Riley

Rong Chang Yan

Khalid ElGalaind

Thomas Jordan

Disclosed are method(s), system(s), and article(s) of manufacture for implementing layouts for an electronic design using machine learning, where users re-use patterns of layouts that have been previously implemented, and those previous patterns are applied to create recommendations in new situations.

Method and system for automatically extracting layout design patterns for custom layout design reuse through interactive recommendations

A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.

Producing a net topology pattern as a constraint upon routing of signal paths in an integrated circuit design

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Pittsburgh, PA, United States of America

Jose A Martinez