Intel Corporation

Jose A Maiz

Jun He

Markus Kuhn

Jihperng Leu

Xiaorong Morrow

Mark T Bohr

Sangwoo Pae

Jack T Kavalieros

Robert S Chau

Suman Datta

Justin K Brask

Qing Ma

Valluri Ramana Rao

Li-Peng Wang

Hyun-Mog Park

Morgan J Dempsey

Gilbert W Dewey

Matthew V Metz

Mark L Doczy

Mark Y Liu

Martin D Giles

David N Shykind

Mitchell C Taylor

Jeffrey E Smith

Thomas N Marieb

Balkaran Gill

Clair C Webb

Zhiyong Ma

Dong S Shim

Avner Kornfeld

Paul McGregor

Todd R Younkin

Carolyn Block

Guanghai Xu

Norbert Roland Seifert

Sarangapani Sista

William M Holt

John Burghard

Gerald S Leatherman

Carmen Campbell

Glen R Wagner

Described is a processor comprising: a plurality of radiation detectors; a first logic unit to receive outputs from the plurality of radiation detectors, the logic unit to generate an output according to the received outputs, the output of the first logic unit indicating whether the processor was exposed to incoming radiations; and a second logic unit to receive the output from the first logic unit, and to cause the processor to perform an action according to the output from the first logic unit.

High dose radiation detector

Biocompatible coatings for implantable medical devices are disclosed. Embodiments of the invention provide methods for coating an object with a biocompatible coating wherein the device is suspended using a flowing gas during the coating process. Embodiments of the invention provide tropoelastin coatings and methods of creating tropoelastin coatings for implantable medical devices. Optionally, the biocompatible coating can be a drug eluting coating.

Biocompatible coatings for medical devices

Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least one via.

Methods of forming electromigration and thermal gradient based fuse structures

Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.

Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects

A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair module determines a bad bit to be repaired within a column based on any individual or combination of factors, such as the number of errors per line of the cache, the number of errors correctable per line of the cache due to error correction code (ECC), the failure rate of bits, or other considerations. The bad bit is transparently repaired by the repair bit mapped to the column including the bad bit, upon an access to a cache line including the bad bit.

Repair bits for a low voltage cache

A microelectronic die including a CMOS ring oscillator thereon, and a method of using the same. The microelectronic die includes: a die substrate; and a plurality of CMOS ring oscillators on the die substrate, the ring oscillators being disposed at regions of the die substrate that are adapted to exhibit differing strain responses to package-included stress with respect to one another. A method of determining mechanical stress on a die which includes providing a die substrate in a CMOS ring oscillator on a die substrate. A frequency counter is coupled to the ring oscillator to measure a frequency of the ring oscillator to generate a frequency data signal therefrom. The frequency data signal is used to determine the mechanical stress on the die at a location of the ring oscillator.

Microelectronic die having CMOS ring oscillator thereon and method of using same

A SOI device features a conductive pathway between active SOI devices and a bulk SOI substrate. The conductive pathway provides the ability to sink plasma-induced process charges into a bulk substrate in the event of process charging, such as interlayer dielectric deposition in a plasma environment, plasma etch deposition, or other fabrication provides. A method is also disclosed which includes dissipating electrostatic and process charges from a top of a SOI device to the bottom of the device. The top and bottom of the SOI device may characterize a region of active devices and a semiconductor method respectively. The method further includes a single masking step to create seed regions for an epitaxial-silicon pathway.

Process charging and electrostatic damage protection in silicon-on-insulator technology

A semiconductor substrate having metal oxide semiconductor (MOS) devices, such as an integrated circuit die, is mechanically coupled to a stress structure to apply a stress that improves the performance of at least a portion of the MOS devices on the die.

Transistor performance enhancement using engineered strains

A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 &#x212b; to 60 &#x212b;. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600&#xb0; C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.

Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer

A method for making a semiconductor device is described. That method comprises adding nitrogen to a silicon dioxide layer to form a nitrided silicon dioxide layer on a substrate. After forming a sacrificial layer on the nitrided silicon dioxide layer, the sacrificial layer is removed to generate a trench. A high-k gate dielectric layer is formed on the nitrided silicon dioxide layer within the trench, and a metal gate electrode is formed on the high-k gate dielectric layer.

Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode

Metal-metal oxide etch stop/barrier for integrated circuit interconnects

An interconnect structure for an integrated circuit having several levels of conductors is disclosed. Dielectric pillars for mechanical support are formed between conductors in adjacent layers at locations that do not have vias. The pillars are particularly useful with low-k ILD or air dielectric.

Interconnect structure for an integrated circuit and method of fabrication

Growing community of inventors

Portland, OR, United States of America

Jose A Maiz