Xilinx, Inc.

Jorn W Janneck

David Bruce Parlour

Ian D Miller

Paul R Schumacher

Christopher H Dick

Pradip Jha

Prasanna Sundararajan

Thomas A Lenart

A computer-implemented method of caching data in a managed runtime computing environment can include loading source data and comparing content of the source data with at least one of a plurality of cache entries. Each cache entry can include a representation of previously received source data and a transformation of the previously received source data. A transformation for the source data from a cache entry can be selected or a transformation for the source data can be generated according to the comparison. The transformation for the source data can be output.

Content-based caching in a managed runtime computing environment

A method of generating data for estimating resource requirements for a circuit design is disclosed. The method comprises identifying a plurality of intermediate circuit modules of netlists for circuit designs; elaborating each intermediate circuit module of the plurality of intermediate circuit modules according to an associated plurality of parameter sets; generating an estimate of resources for each intermediate circuit module and parameter set of the associated plurality of parameter sets; and storing the estimates of resources for the intermediate circuit modules.

Method of generating data for estimating resource requirements for a circuit design

Automatic queue sizing for data flow applications for an integrated circuit is described. Queue sizes for queues of a dataflow network are initialized to a set of first sizes for running as distributed actors without having to have centralized control. If it is determined there is a deadlock, causes for the dataflow network being deadlocked are analyzed with a controller coupled thereto to select a first actor thereof. The first actor of the dataflow network is selected as being in a stalled write phase state. Queue size is incremented for at least one queue of the queues to unlock the first actor from the stalled write phase state. The running, the determining, the analyzing, and the incrementing are iteratively repeated to provide a second set of sizes for the queue sizes sufficient to reduce likelihood of deadlock of the data flow network.

Automatic queue sizing for dataflow applications

In one embodiment, a concurrent processing system is disclosed. For example, in one embodiment of the present invention, a concurrent processing system, comprises a first processing element comprising a first monitor module, a second processing element in communication with the first processing element, the second processing element comprising a second monitor module, and a first system monitor for receiving a notification from at least one of: the first processing element, or the second processing element, wherein the notification indicates an event detected by one of the first monitor module, or the second monitor module.

Method and apparatus for processing an event notification in a concurrent processing system

An asynchronous communication network in an integrated circuit is described. The asynchronous communication network comprises a plurality of circuit elements enabling the transmission of tokens, each circuit element having a component interface comprising: a routing network coupled to a first adjacent circuit element of the plurality of circuit elements; and a control circuit coupled to the routing network, the control circuit having a first input coupled to receive a first command requesting a detection of a token received at a second input of the control circuit, and a first acknowledgement output coupling a first acknowledgement signal indicating whether the first command is received at the first input. Methods of enabling asynchronous communication in an integrated circuit are also disclosed.

Asynchronous communication network and methods of enabling the asynchronous communication of data in an integrated circuit

Method and apparatus for generating an implementation of a program language circuit description for a programmable logic device (PLD) is described. In one example, the program language circuit description is analyzed to identify constructs indicative of dynamic function re-assignment. A hardware description of the program language circuit description is generated. The hardware description includes a plurality of implementations responsive to the identified constructs. Physical implementation data is generated from the hardware description. The physical implementation includes a plurality of partial configurations for the PLD based on the respective plurality of implementations in the hardware description.

Method and apparatus for supporting run-time reconfiguration in a programmable logic integrated circuit

Systems and methods detect a communication received at receiving antennas from transmitting antennas. Each transmitting antenna transmits a symbol in a constellation. A sphere detector performs a depth-first search until the depth-first search terminates in response to a terminate signal requesting the result from the sphere detector. The depth-first search evaluates respective distances of one or mode leaf nodes in response to the communication received at the receiving antennas. The depth-first search selects the result from these nodes in response to the respective distances. The result includes a selected leaf node that identifies a corresponding symbol in the constellation for each transmitting antenna, with this symbol detected as transmitted by the transmitting antenna.

Sphere detector performing depth-first search until terminated

A system detects a communication transmitted from multiple transmitting antennas. The system includes a media access controller and a physical block. Based on a signal to noise ratio (SNR), the allocation circuit of the media access controller assigns a portion of a spectral resource to the communication. The physical block includes multiple receiving antennas for receiving the communication, an estimating circuit for determining the SNR of the communication received at the receiving antennas, and a sphere detector. The sphere detector calculates a respective cost for possible combinations of symbols for the transmitting antennas. The sphere detector calculates the respective costs of the possible combinations from the portion of the spectral resource of the communication received at the receiving antennas. The sphere detector selects one of the possible combinations in response to the respective costs. The system detects the transmitted communication to be the symbols of the selected combination.

Cross-layer allocation of spectral resource to spatially multiplexed communication

A method of evaluating an architecture for an integrated circuit device is disclosed. The method comprises generating a library of primitives for a predetermined architecture; transforming an original dataflow program into an intermediate format; transforming the intermediate format to a dataflow program defined in terms of the predefined library of primitives; and generating an implementation profile comprising information related to an implementation of the original dataflow program in an integrated circuit having the predetermined architecture. A method of evaluating an architecture for an integrated circuit device is also disclosed.

Method of evaluating an architecture for an integrated circuit device

A method of determining a factorization permutation for a natural number can include storing a canonical prime factor vector within memory of a system and storing a first basis vector within the memory. The method can include deriving a first count sequence, including a plurality of counts, from the first basis vector, wherein each count of the first count sequence is a child of the first basis vector. For each count of the first count sequence, a second basis vector can be output that is a child of the count, wherein each count of the first count sequence and child second basis vector specifies a factorization permutation of the natural number.

Generating factorization permutations of natural numbers and performing circuit design exploration

Disclosure is made of approaches for mapping an electronic design specification to an implementation. In one approach, quality metrics are associated with functional units of the design, and the functional units are mapped to respective initial implementations. For each functional unit a respective quality indicator is determined based on the mapping. The quality indicator specifies a degree to which the functional unit achieves the associated quality metric. At least one of the functional units is selected for remapping based on the quality indicator of that functional unit or the quality indicator of another functional unit. An alternative implementation to the initial implementation is selected for each selected functional unit to improve the quality indicator. The selected functional unit is remapped to the selected alternative implementation.

Automated method of architecture mapping selection from constrained high level language description via element characterization

A method of estimating resource requirements for a circuit design is disclosed. The method comprises identifying intermediate circuit modules of a netlist associated with the circuit design; accessing a library of resource requirements for intermediate circuit modules of netlists for circuit designs; selecting intermediate circuit modules of the library according to predetermined parameters for the circuit design; and generating an estimate of resource requirements for the circuit design based upon resource requirements of the selected intermediate circuit modules.

Method of estimating resource requirements for a circuit design

Dataflow control for an application with timing parameters, including interfacing temporal and non-temporal domains, is described. The domains receive input data to a first dataflow network block, which is processed for untimed output of first tokens. The first tokens are obtained by a memory interface for timed writing of data portions of the first tokens to data storage and for timed reading of the data portions therefrom. Sending of the data portions read to a first queue of a first controller block is untimed, and the data portions are output by the first controller block with physical timing parameters. Second tokens are generated by the first controller block responsive to the physical timing parameters. The second tokens are fed back to a second queue of the first dataflow network block to control rate of generation of the first tokens by the first dataflow network block.

Dataflow control for application with timing parameters

Method and apparatus for processing a dataflow description of a digital processing system is described. In one example, a model of the dataflow description is simulated. Computational steps performed during the simulation and actual dependencies among the computational steps resulting from the simulation are identified. Causation trace data is generated in response to the step of recording. The causation trace data may then be analyzed using one or more analyses to produce quantitative data that characterizes the dataflow description.

Method and apparatus for processing a dataflow description of a digital processing system

A signal processing network and method for generating code for such a signal processing network are described. Pipeline blocks are each coupled to receive control signaling and associated information signaling from a scheduler. Each of the pipeline blocks respectively includes an allocation unit, a pipeline, and section controllers. The allocation unit is configured to provide a lock signal and sequence information to the section controllers in each of the pipeline blocks. The section controllers are configured to maintain in order inter-pipeline execution of the sequence responsive to the sequence information and the lock signal.

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San Jose, CA, United States of America

Jorn W Janneck