Maxim Integrated Products, Inc.

Mija Industries, Inc.

Jorge Rubinstein

Albert Rooyakkers

John J McSheffrey

Robert M Manning

A power management system and method including a normally-open switch, an on/off circuit, a microprocessor, and at least one sensor to monitor a condition. The on/off circuit includes an on/off control gate-controlled switch device such as a PMOS device for system power, a flip/flop switch to respectively activate and deactivate the on/off control PMOS device, and a transition detection circuit connected to the normally-open switch. A single DC power source establishes a source voltage to power the on/off circuit and the normally-open switch. The transition detection circuit generates an 'on' signal when the user initially activates the normally-open switch, and supplies the 'on' signal to the flip/flop switch to change it to an &#x201c;on&#x201d; state to activate the on/off control PMOS device. While activated, the on/off control PMOS device enables system power from the power source to be provided to at least the sensor and the microprocessor. The microprocessor generates an &#x201c;off&#x201d; signal when the normally-open switch is activated for at least a selected period of time, and supplies the &#x201c;off&#x201d; signal to the flip/flop switch to change it to an &#x201c;off&#x201d; state to deactivate the on/off control PMOS device and thereby disable system power to at least the sensor and the microprocessor.

Power management system for pressure monitoring

Embodiments of the present invention are directed to parallel, pipelined, integrated-circuit implementations of computational engines designed to solve complex computational problems. One embodiment of the present invention is a family of video encoders and decoders ('codecs') that can be incorporated within cameras, cell phones, and other electronic devices for encoding raw video signals into compressed video signals for storage and transmission, and for decoding compressed video signals into raw video signals for output to display devices. A highly parallel, pipelined, special-purpose integrated-circuit implementation of a particular video codec provides, according to embodiments of the present invention, a cost-effective video-codec computational engine that provides an extremely large computational bandwidth with relatively low power consumption and low-latency for decompression and compression of compressed video signals and raw video signals, respectively.

Parallel, pipelined, integrated-circuit implementation of a computational engine

Embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by, parallel, pipelined, integrated-circuit implementations of computational engines designed to solve complex computational problems. Additional embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by, a variety of different types of electronic devices. One embodiment of the present invention comprises a memory controller implemented in a first integrated circuit or other electronic system and one or more separate memory devices. Alternative embodiments of the present invention incorporate the memory controller within one or more memory devices that are connected to, and accessed by, an integrated-circuit-implemented computational engine or another electronic device. In alternative embodiments of the present invention, the memory controller and memory are together integrated within a computational engine or another electronic device. Alternative embodiments of the present invention include a multi-access memory that interfaces to a simpler memory controller for connection to, or integration within, a computational engine or other electronic device.

Memory subsystem

Embodiments of the present invention relate to a multi-bus architecture within a video codec that discretely and efficiently transports video components within the codec. This multi-bus architecture provides a relatively more efficient transport mechanism because the various buses are designed to specifically address unique characteristics of the video components or parameters being processed within the codec.

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Newton, MA, United States of America

Jorge Rubinstein