Intel Corporation

Jorge Eduardo Parra Osorio

Subramaniam M Maiyuran

Guei-Yuan Lueh

Wei-Yu Chen

Chandra S Gurram

Vikranth Vemulapalli

Supratim Pal

Shuai Mu

Provision of multiple register allocation sizes for threads is described. An example of a system includes one or more processors including a graphics processor, the graphics processor including at least a first local thread dispatcher (TDL) and multiple processing resources, each processing resource including a plurality of registers; and memory for storage of data for processing, wherein the one or more processors are to determine a register size for a first thread; identify one or more processing resources having sufficient register space for the first thread; select a processing resource of the one or more processing resources having sufficient register space to assign the first thread; select an available thread slot of the selected processing resource for the first thread; and allocate registers of the selected processing resource for the first thread.

Multiple register allocation sizes for threads

Growing community of inventors

El Dorado Hills, CA, United States of America

Jorge Eduardo Parra Osorio