U.S. Philips Corporation

Jorg Wolber

Klaus G Kroner

Dieter J Kunze

Gerd Onken

Thomas Suwald

Walter H Demmer

Hartmut S Harlos

Friedrich E Hahn

Matthias Peters

Karl Gedl

Sonke Struck

Ulrich Mohlmann

Cord-Heinrich Bartels

A comb filter arrangement comprising at least one delay circuit and an adder, this adder being twice supplied with a video signal modulated on a carrier, which video signals are applied mutually shifted with time. The signals are delayed by the delay circuits, so that either video signal applied to the adder is delayed relative to the other video signal by a given period of time. Furthermore, the delay circuits are arranged in switched capacitor technique.

Comb filter arrangement

A circuit arrangement for processing an input video signal (V) is described, which video signal has a fixed black level (SP), a given white peak value (WW) as well as a black peak value (SW) dependent on the picture contents (during tb), in which a correct display of the blackest and brightest parts of the picture contents of the video signal (V) is rendered possible without many components and without interference. To this end the circuit arrangement includes

Contrast and brightness control whereby both are based on the detected

A digital phase-locked loop (PLL) which responds to a square-wave input signal of on expected frequency f.sub.E and comprises a change-over switch which is switched in response to square-wave signals or different frequencies and precedes a main divider operating with a divisor D and which produces the output signal of the phase-locked loop. The change-over switch is activated as a function of the output signal and the input signal. In order to provide symmetrical locking in of the phase-locked loop and a small capture-and-hold range, the change-over switch is switched between a first square-wave signal of the frequency f.sub.1, a second square-wave signal of the second frequency f.sub.2 and a third square-wave signal of the frequency f.sub.3, in which:

Digital phase-locked loop

A multiplying digital-to-analog converter which includes an R-2R chain network is characterized in that, for partial or complete potential equalization, the chain network for an n-bit-wide digital signal applied to the converter comprises (n+m) connection points, where n,m are natural integers greater than zero, the connection point (n+m) produces the output signal of the converter. A first current mirror is provided which produces a constant first current that can be switched to the individual connection points (1+m) to (n+m). The least significant bit of the digital signal is allocated to the connection point (1+m) and the most significant bit to the connection point (n+m) and the first current is switched only to those connection points whose allocated bit has a first state. A second current mirror is provided which produces a constant second current that is larger than that of the first current mirror and can be switched to the individual connection points 1 to n, while the least significant bit is allocated to the connection point 1 and the most significant bit to the connection point n, the second current is switched only to those connection points whose allocated bit has a second state.

Multiplying digital-to-analog converter

A circuit arrangement for amplifying a periodic signal and for adjusting a reference level contained therein, in which a charging/discharging arrangement alternately supplies charging or discharging currents to a storage means, depending on whether the value of a periodic signal exceeds or is exceeded by a limit value, such that a mean value at least substantially corresponding to the reference level occurs at the storage means includes a compensator means which adjusts the charging and disharging currents by a compensation factor which is selected such that the ratio of the charging current to the discharging current is independent of fluctuations in current resulting from variations affecting the gain factors of amplifier components comprised in the amplifier means.

Circuit arrangement for adjusting a reference level in a periodic signal

A circuit arrangement for deriving an output current from an input current, which output current is limited to a current range which is bounded by at least one limit value. It is possible to limit high-frequency currents by avoiding current distributions or saturation effects in that the circuit arrangement comprises a current combination element (1) for forming an at least substantially linear combination of the input current (IE), the output current (IA) and a fixed reference current (IR) and by at least a rectifier circuit (2) arranged in the current path of the input current (IE) and/or the output current (IA).

Circuit arrangement for generating a limited current

A circuit arrangement for transferring a d.c. voltage via a smoothing network including a capacitor which can be switched to prevent a surge in the transferred signal from occurring. The voltage from the output terminal is applied to the capacitor in the changed-over state via an amplifier having a high input impedance and a gain factor of substantially 1.

Switchable smoothing network

The invention relates to a circuit arrangement for a video recorder which derives a line frequency signal from a pulse-shaped oscillator signal by means of a plurality of frequency dividers. The arrangement comprises a first section suitable for VHS or Video-8 video recorders in conformity with the or NTSC standard and a second section adapted to the relevant standard.

Circuit arrangement for frequency division

A circuit arrangement for a video recorder comprises a modulator (5) for modulating a chrominance signal from a first onto a second carrier wave by means of a third carrier wave. In order to generate the third carrier wave a first mixer (39) is coupled to a reference oscillator (18) and to a first voltage-controlled oscillator (23). A control signal from a phase-comparator circuit (15), which compares the frequency and phase of the burst signal with these of the first oscillator signal, and a control signal from a phase-comparator circuit (30) of a phase-locked loop in which a second voltage-controlled oscillator (27) is synchronized with the line synchronizing pulses, are applied to the first voltage-controlled oscillator (23). The two voltage-controlled oscillators are substantially identical and have a fixed frequency ratio with each other.

Circuit arrangement for a video recorder

A circuit arrangement for a color image recording and reproduction instrument(video recorder) or a color television receiver. Such devices have a phase regulation circuit in which an oscillator (18, 59) is controlled in accordance with the phase comparison between the color synchronization signal and a reference signal performed in a phase comparator circuit (9, 40). A control signal from the phase comparator circuit is applied to at least two scanning and locking units (12, 13; 49 to 52) which can be changed over successively and cyclically. These units scan the control signal during the color synchronization blanking time. The output signals of the scanning and locking units (12, 13; 49 to 52) are applied to an adder (16, 54) coupled to the oscillator (18, 59). The interference signals arising from the changeover and superimposed on the control signal are thus eliminated.

Circuit arrangement for a color image recording and reproduction

A charging current source and a discharging current source are alternately connected to an input capacitor. By choosing the current ratios it is possible to switch a reference level located in the signal range, for example the black level in a television signal, in the circuit, without the necessity for interval keying.

Circuit arrangement for adjusting the direct current level of a video

A line sawtooth deflection current generator with modulating means for the purpose of correcting the amplitude variations of the current produced, the said modulating means including a stage operating in the switching mode, a switch of which is connected via a smoothing inductance. A winding coupled to an inductance in the deflection circuit is provided in the branch of the smoothing inductance between the scan capacitor and the switch.

Line sawtooth deflection current generator

A circuit is shown for compensating for rapid changes in D.C. levels in high pass filter coupled vertical deflection circuits. It features a second high pass filter that applies a D.C. signal having a second level change so that the first change is cancelled out. The second change can be applied directly to the first change with opposite polarity, or to the emitter of a transistor that receives the first change at its base with the same polarity.

Circuit arrangement for transmitting an alternating current oscillation

A circuit arrangement in television display apparatus for deforming a sawtooth signal, for example, for the S correction, including a plurality of difference amplifiers having a common input terminal and a common output terminal.

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Pinneberg, Germany

Jorg Wolber