Infineon Technologies Ag

Jörg Kliewer

Manfred Pröll

Stephan Schröder

Ralf Schneider

Herbert Benzinger

Georg Erhard Eggers

Claus Engelhardt

Martin Versen

Norbert Wirth

Aurel Von Campenhausen

Koen Van Der Zanden

Jürgen Auge

Frank Schroeppel

Rupert Lukas

Björn Wirker

Jan Spitz

An integrated semiconductor memory device includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense amplifier, where each memory cell includes a selection transistor and a storage capacitor. The storage capacitor of each memory cell includes a first capacitor electrode and a second capacitor electrode, and the selection transistor of each memory cell includes a first source/drain region that is connected by a first contact connection to one bit line of a pair of bit lines corresponding with the memory cell, and a second source/drain region that is conductively connected to the first capacitor electrode of the storage capacitor of the memory cell. The second capacitor electrode of the storage capacitor of each memory cell is connected to the other bit line of the pair of bit lines corresponding with the memory cell.

Integrated semiconductor memory and method for operating a semiconductor memory

The invention relates to a test method for determining a wire configuration for a circuit carrier having at least one component arranged thereon, where internal lines in the component are connected to component connections in a prescribed order, and where the component connections are wired to connections on the circuit carrier. According to the method, a respective prescribed test signal is applied to each internal line of the component using a controllable test signal generator integrated in the component. Output signals applied to the connections of the circuit carrier are tapped off. Thereafter, the respective output signals tapped off are identified with the corresponding test signals applied to the internal lines of the component using an external test apparatus for determining the wire configuration between the component connections and circuit carrier connections.

Test method for determining the wire configuration for circuit carriers with components arranged thereon

An integrated semiconductor memory includes a memory cell array with at least one memory cell, in which a data value is stored, and an evaluation circuit with a counter. During a test of the integrated semiconductor memory, a counter reading of the counter is altered if the data value stored in the memory cell deviates from a desired value. A threshold value is predefined by a control circuit. A programming circuit compares the threshold value on the input side with the instantaneous counter reading of the counter. If the counter reading of the counter exceeds the threshold value, a programming element changes from a first programming state to a second programming state. After the conclusion of the test, the state of the programming element is read out via an output terminal. This scheme makes it possible to deduce a possible cause of failure of the integrated semiconductor memory.

Integrated semiconductor memory

An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage (Vout). A first branch including a first controllable resistance (T) and a second branch including a charge pump () and a second controllable resistance (T) are connected between the input terminal (IN) and the output terminal (A). A control circuit () alters the resistance values of the first and second controllable resistances (T, T) in a manner dependent on a ratio of an actual value (Vout) of the output voltage to a desired value (VSout) of the output voltage and a ratio of an actual value (Vext) of the supply voltage to a desired value (VSext) of the supply voltage. As a result, the output voltage (Vout) can be stabilized to the desired value (VSout) virtually independently of fluctuations of the supply voltage.

Integrated circuit for stabilizing a voltage

An integrated memory has individually addressable normal and redundant units of memory cells. A memory unit is used to store, in a normal mode, an address for one of the normal units which needs to be replaced by one of the redundant units. A comparison unit compares an address which is present on an address bus with an address stored in the memory unit and activates one of the redundant units in the event of a match being identified. The memory also has a test circuit which can be activated by a test mode signal, can reset the memory unit to an initial state, and can store an address for one of the redundant units in the memory unit for subsequently writing an identification code to this redundant unit.

Integrated memory having redundant units of memory cells and method for testing an integrated memory

An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word line. A word line driver is coupled to the word line. The word line driver provides a first electrical potential or a second electrical potential to the word line such that the word line is activated by the first electrical potential and is deactivated by the second electrical potential. A passive component (e.g., a diode or a resistor) is coupled between the word line and the second electrical potential such that the word line is coupled to the second electrical potential in a high-resistance fashion through the passive component. The passive component is transmissive for a leakage current between the word line and the contact connection.

Integrated semiconductor memory comprising at least one word line and comprising a multiplicity of memory cells

An integrated semiconductor memory can be operated in a normal operating state synchronously with a control clock. In the test operating state, the integrated semiconductor memory is driven synchronously with a clock edge of the control clock with a first control signal and starts a test run independent of the control clock. Driving with the first control signal, selection transistors in a memory bank that can be selected by a memory bank address are turned off. Afterward, bit lines in the selected memory bank are interconnected and driven with a predetermined precharge potential. After a precharge time has elapsed, one of the word lines is selected by an applied word line address and the selection transistors in the selected memory bank connected to the selected word line are turned on. Precharge times are set and tested independently of the clock period of the control clock.

Method for testing an integrated semiconductor memory

The present invention provides an apparatus for signaling that a predetermined time value has elapsed, having a device for acquiring and storing the amplitude value of a clock signal at an acquisition instant in the temporal profile of the clock signal. A device is provided for continuously comparing the acquired and stored amplitude value of the clock signal with an instantaneous amplitude value of the clock signal and for outputting a comparison signal which has a first logic state if the instantaneous amplitude value of the clock signal is less than the stored amplitude value and has a second logic state if the instantaneous amplitude value of the clock signal is greater than the stored amplitude value. A device is also provided for counting the number of logic states of the comparison signal which occur after the acquisition instant, and for signaling that the predetermined time value has elapsed if the counted number of logic states is equal to a predetermined number of logic states which corresponds temporally to the predetermined time value.

Apparatus for signaling that a predetermined time value has elapsed

An integrated semiconductor memory device includes a memory cell array (B) with a first bit line and a second bit line (BL, /BL), a controllable resistor (SW) and a control unit () configured to control the controllable resistor. In a first operating state of the integrated semiconductor memory device, the first and second bit lines are connected to one another via a first controllable switch (ET) and also via the controllable resistor (SW) which has been set to a low resistance, to a connection (A) that applies a mid-voltage (V), where the voltage level of the mid-voltage is in the form of an arithmetic mean between a first and second voltage potential (VBLH, VBLL). By virtue of the control unit briefly setting the controllable resistor to a very low resistance in the first operating state of the integrated semiconductor memory device, the period of time required for the first and second bit lines require to assume the mid-voltage (V) is shortened. The influence of capacitive coupling influences, which slow down the charging of the first and second bit lines to the mid-voltage, is significantly reduced as a result.

Integrated semiconductor memory device and method for operating an integrated semiconductor memory device

An integrated dynamic memory includes memory cells which are combined to form individual independently addressable units, and a control circuit for controlling a refresh mode for the memory cells. The memory cells can have their memory cell content refreshed. The control circuit is designed such that one or more units of memory cells can be subject to a refresh mode in parallel in a refresh cycle. The control circuit sets a number of memory cell units, which are to be refreshed in parallel in a refresh cycle based on a temperature reference value. A maximum possible operating temperature for a memory chip can be increased without additional restrictions on memory access.

Integrated dynamic memory having a control circuit for controlling a refresh mode for memory cells

A dynamic RAM semiconductor memory with a shared sense amplifier organization concept, in which the cell arrays are subdivided into blocks whose bit lines are connected in pairs from two adjacent blocks in each case to a common sense amplifier and the sense amplifiers are disposed between the cell blocks. In which case bit line switches are disposed in sense amplifier strips&#x2014;lying between the blocks&#x2014;between in each case two adjacent sense amplifiers in order to momentarily connect the other ends&#x2014;not connected to the sense amplifiers&#x2014;of two bit line pairs from the adjacent cell blocks during a precharge phase of a bit line pair activated directly beforehand. The precharge phase takes place at the start of a charge equalization phase.

Dynamic RAM semiconductor memory and method for operating the memory

A frequent problem that arises in particular with regard to the analysis of memory components is that the memory components have to be tested under realistic conditions in a real application environment. In practice, such components are normally firmly soldered in on a module carrier. Owing to the thermal load during soldering, this solution cannot always be used and, furthermore, the contacts that are made should be detachable. Commercially available contact bases with detachable contacts cannot be used, however, since their dimensions are too large and they do not fit in the available surface area on the module carrier. The novel contact base is sufficiently small that a plurality of contact bases can be arranged closely one next to the other in a row in a very small space on a module carrier. The module carrier has plug contacts to be plugged into a commercial socket in order to make contact.

Contact base with detachable contacts for making electrical contact with an electronic component, in particular a multipin electronic component, and module carrier

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Munich, Germany

Jörg Kliewer