International Business Machines Corporation

Jordan Ross Keuseman

Malcolm Scott Allen-Ware

Guillermo Jesus Silva

Todd Jon Rosedahl

Timothy Glen Hallett

Karthick Rajamani

Michael Lee Miller

Charles Robert Lefurgy

Alan J Drake

Patrick Kevin Egan

Heather Lynn Hanson

James Douglas Jordan

Benjamin W Mashak

Glenn Rueban Miles

Martha Broyles

Mark James Jeanson

George Russell Zettles, Iv

John Steven Dodson

Kenneth Lee Wright

Gregory Scott Still

Srinivasan Ramani

Kevin Robert Covi

Jonathan Michael Allen

Justin E Henspeter

Malcom S Allen-Ware

Richard Holmquist

A discrete VRM card comprises a set of VRM controllers. The set of VRM controllers comprises a VRM controller with two feedback loops. The VRM card comprises a power stage and a power-stage critical-signal multiplexer. The output of the power-stage critical-signal multiplexer determines a feedback loop with which the power stage communicates. The VRM card also comprises a configuration selector. The configuration selector determines a feedback-loop assignment for the power-stage critical-signal multiplexer and provides VRM instructions to the VRM controller.

Configurable VRM card

A distributed power management system is configured determine a node power consumption of a node during a first time interval. The system can determine a node power cap. The system can determine a proportional component power budget for a component of the node based, at least in part, on the node power consumption and a component power consumption. The system can determine a power budget for the component for a second time interval based, at least in part on the proportional component power budget.

Distributed power budgeting

It is determined that a current node power consumption for a node is greater than a node power cap that defines a limit of power consumption for the node. Responsive to the current node power consumption being greater than the node power cap and until the current node power consumption is less than the node power cap, power reduction operations are performed. The power reduction operations comprise determining a power management zone of a plurality of power management zones having a lowest priority among the power management zones and having a power cap greater than a minimum power cap for the power management zone. The power reduction operations further comprise setting the power cap for the power management zone to a value less than a prior value assigned as the power cap for the power management zone.

Computer program product and a node implementing power management by associated power management controllers based on distributed node power consumption and priority data

Method performed by an associated power management controller of a zone based on node power consumption and priority data for each of the plurality of zones

A zone power cap for a power management zone that defines a limit of power consumption for the power management zone is determined. The power management zone comprises a plurality of components, wherein the power management zone is associated with a controller. A set of one or more characteristics of a workload associated with the power management zone is determined. A component power cap for one or more of the plurality of components is set based, at least in part, on the set of one or more characteristics of the workload and the zone power cap.

Distributed power management system with plurality of power management controllers controlling zone and component power caps of respective zones by determining priority of other zones

A method, system, and computer program product for system-wide power conservation using memory cache are provided. A memory access request is received at a location in a memory architecture where processing the memory access request has to use a last level of cache before reaching a memory device holding a requested data. Using a memory controller, the memory access request is caused to wait, omitting adding the memory access request to a queue of existing memory access requests accepted for processing using the last level of cache. All the existing memory access requests in the queue are processed using the last level of cache. The last level of cache is purged to the memory device. The memory access request is processed using an alternative path to the memory device that avoids the last level of cache. A cache device used as the last level of cache is powered down.

System-wide power conservation using memory cache

A distributed power management computer program product is configured to collect power consumption data that indicates power consumption by at least a plurality of the components of a node. The program code can be configured to provide, to each of a plurality of controllers associated with a respective one of the plurality of components, the power consumption data. The program code can be configured to determine a node power consumption. The program code can be configured to determine a power differential as a difference between the node power consumption and an upper power consumption threshold of the node. The program code can be configured to determine a proportion of the node power consumption consumed by a first component. The program code can be configured to compute a local power budget for the first component.

Embodiments include collecting, from each of a plurality of controllers of a node having a plurality of components, component power consumption. Each of the plurality of controllers is associated with one or more of the components. The component power consumptions are provided to the controllers. A node power consumption for the node is determined based, at least in part, on the component power consumption. The power cap is determined for the plurality of components. A power differential power is determined as a difference between the node power consumption and the power cap for the plurality of components. A proportion of the node power consumption consumed by the component is determined based on the component power consumption of the component. A local power budget is computed for the component based, at least in part, on the power differential and the proportion of the node power consumption consumed by the component.

A method and apparatus are provided for implementing dynamic regulator output current limiting. An input power to the regulator is measured, and the measured input power is related to a regulator output current and a regulator over current trip point, and dynamically used for providing dynamic regulator output current limiting.

Implementing dynamic regulator output current limiting

A power regulation scheme includes a first voltage regulation portion having a first voltage regulator, a second voltage regulator, and a switching system. The first voltage regulation portion is connected in parallel with a second voltage regulation portion. The second voltage regulation portion regulates an input voltage if an open condition occurs within the first voltage regulation portion. The switching system forces the second voltage regulator to regulate the input voltage if a short condition occurs within the first voltage regulator.

Multiple branch alternative element power regulation

An electronic system having a spread spectrum clock is disclosed. A spread spectrum clock source creates and transmits both a spread spectrum clock signal and a modulation signal. A spread spectrum clock generator uses a modulation waveform on the modulation signal to frequency modulate a reference oscillator frequency. A logic unit comprises a Phase Locked Loop that receives the spread spectrum clock signal and the modulation signal and generates a logic unit clock signal.

Spread spectrum clocking with transmitted modulation

A power regulation scheme includes a first voltage regulation portion connected in parallel with a second voltage regulation portion that regulates a voltage if an open condition occurs within the first voltage regulation portion. Each voltage regulation portion may include a first voltage regulator connected in series with a second voltage regulator that regulates the voltage if a short condition occurs within the first voltage regulator. Each voltage regulation portion may utilize a switching element to route an output voltage of the first voltage regulator past the second voltage regulator if the output voltage has been regulated and/or to force the output voltage to be regulated by the second voltage regulator if the output voltage has not been regulated.

A computer implemented method employs software on a system for generating a logical representation of an electronic circuit undergoing a design. A predetermined grid for the circuit being designed is selected through interaction with the user through a graphical user interface. An input file defines objects to be plotted to the grid, and is read into a computer system. Objection locations relative to the grid, and connections between objects are checked and adjustments made by moving objects as necessary to align with the grid and to ensure connections between the objects. A design file of the adjusted logical representation is written for use in completing a circuit design.

User selected grid for logically representing an electronic circuit

A power regulation circuit includes at least a first regulator connected to a second regulator in series forming a first regulator pair and a third regulator connected to a fourth regulator in series forming a second regulator pair. The first regulator pair is connected in parallel with the second regulator pair. Each individual regulator is configured to separately regulate an input voltage to a predetermined regulated output voltage. The second regulator pair regulates the input voltage if a short condition occurs within the first regulator pair and the second and fourth regulators each regulate the input voltage if an open condition occurs within the first or third regulator respectively.

Growing community of inventors

Rockester, MN, United States of America

Jordan Ross Keuseman