Micron Technology Incorporated

USA as Represented by Secretary of the Navy

Battelle Energy Alliance, LLC

Jordan D Greenlee

John David Hopkins

Everett Allen McTeer

Rita J Klein

John Mark Meldrim

Alyssa N Scarbrough

Daniel Billingsley

Yongjun Jeff Hu

Nancy M Lomeli

Collin Howder

Jiewei Chen

Lifang Xu

Xiao Li

David Ross Economy

Yiping Wang

Tom George

Indra V Chary

Shuangqiang Luo

Swapnil Lengade

Christian George Emor

Shyam Surthi

Brenda D Kraus

Chet E Carter

Justin D Shepherdson

E Allen McTeer

Francis J Kub

Matthew J King

David A Daycock

Travis J Anderson

Christopher W Petz

Silvia Borsari

Boris N Feigelson

Minsoo Lee

Peng Xu

Purnima Narayanan

Andrew Li

Vinayak Shamanna

Sidhartha Gupta

Luca Fumagalli

Marko Milojevic

Kyle A Ritter

Benben Li

Jun Fang

Tao D Nguyen

Rithu K Bhonsle

Liu Liu

Aaron Kenneth Belsher

Narula Bilik

Naiming Liu

Rajesh Balachandran

Brian S Beatty

Chieh Hsien Quek

Kaiming Luo

Scott M Pook

Vladimir Samara

Amritesh Rai

Travis Rampton

Giovanni Mazzone

Everett A Mcteer

John A Smythe

Rajasekhar Venigalla

Allen McTeer

Karl D Hobart

Farrell Martin Good

Marko J Tadjer

Andrew D Koehler

Damir Fazil

Francois H Fabreguette

M Jared Barclay

Yifen Liu

Eugene A Imhoff

Robert E Stahlbush

Shen Hu

Boris N Feygelson

Mithun Kumar Ramasahayam

Nadeemullah A Mahadik

Anurag Jindal

Jing Wai Fong

Song Kai Tan

Aaron P Thurber

Sijia Yu

Aireus Christensen

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. A lower of the first tiers comprises sacrificial material. A horizontally-elongated slot is formed through the first and second tiers to the sacrificial material in individual of the memory-block regions to form laterally-spaced sub-block regions in the individual memory-block regions. The sacrificial material is isotropically etched from the lower first tier through the horizontally-elongated slots. After the isotropic etching, conducting material is formed in the horizontally-elongated slots and in the lower first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. After forming the conducting material, horizontally-elongated trenches are formed through the first tiers and the second tiers and that are individually laterally between immediately-adjacent of the memory-block regions. Other embodiments, including structure independent of method, are disclosed.

Method used in forming a memory array comprising strings of memory cells comprising forming trenches between memory-block regions after forming trenches to form laterally-spaced sub-block regions in the memory-block regions

A microelectronic device includes a source stack, a source contact vertically adjacent to the source stack, a semiconductor material vertically adjacent to the source contact, tiers of alternating conductive materials and dielectric materials vertically adjacent to the semiconductor dielectric material, a dielectric structure within a slot structure and extending through the tiers of the microelectronic device to the source contact of the microelectronic device, oxide cap structures laterally between the semiconductor material and the dielectric structure, and pillars extending through the tiers, the semiconductor material, and the source contact and into the source stack. Related electronic systems and methods are also disclosed.

Microelectronic devices including cap structures, and related electronic systems and methods

Methods, systems, and devices for staircase formation in a memory array are described. A liner composed of a first liner material may be deposited on a tread and a first portion of the liner may be doped. After doping the first portion of the liner, a second portion of the liner may be converted into a second liner material using a chemical process. After converting the second portion of the liner into the second liner material, the first portion of the liner material may be removed so that a subsequent removal process can expose a first sub-tread. After exposing the first sub-tread, the second portion of the liner may be removed so that a second sub-tread is exposed.

Staircase formation in a memory array

Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and said other region, and separates a first memory-block-region from a second memory-block-region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. Rings laterally surround lower regions of the conductive posts. The rings are between the conductive posts and the doped-semiconductor-material. The rings include laminates of two or more materials, with at least one of said two or more materials being insulative. Some embodiments include methods for forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel material strings extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair step region comprises a cavity comprising a flight of stairs having insulative material atop stair treads. Individual of the treads comprise conducting material of a conductive tier. Conductive vias extend through the insulative material and are directly above and against the conducting material of the respective individual tread. A lining is over sidewalls and bottom of the individual conductive vias. The individual conductive vias are directly under the bottom of the lining directly above the conducting material of the respective individual tread. Other embodiments, including methods of forming the circuitry and elements of circuitry above, are disclosed.

Memory circuitry and method used in forming memory circuitry

A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The channel material of individual of the channel-material strings is directly electrically coupled to the conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises insulating material. The conductor material in the conductor tier comprises a pair of side interfaces that individually extend downwardly from a top of the conductor tier on one of opposing sides of the intervening material and individually extend longitudinally-along the immediately-laterally-adjacent memory blocks. The side interfaces have the conductor material laterally-over opposing sides thereof. Other embodiments, including method, are disclosed.

Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Individual of the conductive tiers comprise laterally-outer edges comprising conductive molybdenum-containing metal material extending horizontally-along its memory block. Channel-material strings extend through the insulative tiers and the conductive tiers. At least one of conductive or semiconductive material is formed extending horizontally-along the memory blocks laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material that extends horizontally-along its memory block. Insulator material extending horizontally-along the memory blocks is formed laterally-outward of the at least one of the conductive or the semiconductive material that is laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material. Other embodiments, including structure independent of method, are disclosed.

Methods used in forming a memory array comprising strings of memory cells and memory arrays comprising strings of memory cells

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a first vertical stack comprising vertically-alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. A second vertical stack is aside the first vertical stack. The second vertical stack comprises insulative tiers collectively comprising at least two different compositions relative individual of the insulative tiers. Individual of the at least two different compositions comprise silicon nitride. One of the individual different compositions comprise carbon-doped silicon nitride having at least 0.5 atomic percent more carbon than atomic percent of carbon, if any, in the silicon nitride of another of the individual different compositions. Other embodiments, including method, are disclosed.

Methods used in forming memory arrays having strings of memory cells

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed and individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor material between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material that is laterally-between the horizontally-elongated lines. After the horizontally-elongated lines are formed, conductive material of a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier, Other embodiments, including structure independent of method, are disclosed.

Some embodiments include a method of forming a conductive structure. A metal-containing conductive material is formed over a supporting substrate. A surface of the metal-containing conductive material is exposed to at least one radical form of hydrogen and to at least one oxidant. The exposure alters at least a portion of the metal-containing conductive material to thereby form at least a portion of the conductive structure. Some embodiments include a conductive structure which has a metal-containing conductive material with a first region adjacent to a second region. The first region has a greater concentration of one or both of fluorine and boron relative to the second region.

Metal-containing structures, and methods of treating metal-containing material to increase grain size and/or reduce contaminant concentration

A microelectronic device comprises a stack structure, a contact structure, a liner material, and a boron-containing material. The stack structure comprises alternating conductive structures and dielectric structures. The contact structure extends through the stack structure. The liner material is between the stack structure and the contact structure. The boron-containing material is between the liner material and the stack structure. Related electronic systems and methods are also described.

Microelectronic devices comprising a boron-containing material, and related electronic systems and methods

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor tier between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material and comprise metal material. After the horizontally-elongated lines are formed, conductive material is formed in a lower of the first tiers and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.

Methods, systems, and devices for self-aligned etching techniques for memory formation are described. A memory device may include a stack of alternating materials and a pillar extending through the stack of alternating materials, where the stack of alternating materials and the pillar may form a set of multiple memory cells. A polysilicon material may be formed above the pillar, where the polysilicon material may be associated with a selector device for the memory cells. A masking material may be formed above the polysilicon material and the stack of alternating materials, where the masking material may be aligned with the polysilicon material and may have a width that is greater than a width of the polysilicon material and the pillar. The masking material may prevent the polysilicon material, the pillar, and a portion of the stack of alternating materials beneath the masking material from being removed during an etching operation.

Self-aligned memory architecture comprising a memory array associated with pillars and polysilicon material

A microelectronic device comprises conductive structures and insulative structures vertically alternating with the conductive structures. At least one of the insulative structures includes interfacial regions extending inward from vertical boundaries of the at least one of the insulative structures, and central region vertically interposed between the interfacial regions. The interfacial regions are doped with one or more of carbon and boron. The insulative structures comprise a lower concentration of the one or more of carbon and boron than the interfacial regions. Additional microelectronic devices, electronic systems, and methods are also described.

Microelectronic devices including stack structures having doped interfacial regions, and related systems and methods

Methods, systems, and devices for a barrier structure for preventing removal of, such as etching to, control circuitry are described. A memory device may include control circuitry over a substrate and for accessing a memory array and contact regions configured to couple with the control circuitry. The memory device may include barrier regions between respective contact regions that includes a barrier material. The memory device may include a stack of layers over the barrier region and the contact regions that is associated with the memory array, and the barrier material may prevent a removal (e.g., an etch) through the stack of layers and at least partially between contact regions from extending to the control circuitry.

Barrier structure for preventing etching to control circuitry

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Boise, ID, United States of America

Jordan D Greenlee