Samsung Electronics Co., Ltd.

Joosung Yun

Jihyun Choi

Seongseob Shin

Moon-Ho Lee

Soonil Kwon

Seong-Gwon Jang

Woonsup Choi

A test board includes a board substrate, a connector at a side of the board substrate, a plurality of device-under-test (DUT) boards which are connected to the board substrate and on which semiconductor devices are mounted as DUTs, and a plurality of DC-DC converters connected to the plurality of DUT boards. The plurality of DC-DC converters convert an input voltage supplied thereto via the connector into operating voltages, and provide the operating voltages to the semiconductor devices on the plurality of DUT boards corresponding thereto. The operating voltages are substantially the same.

Test board having semiconductor devices mounted as devices under test and test system including the test board

A memory device includes a memory cell array, a peripheral circuit, a test mode register set, and a test circuit. The peripheral circuit stores data in the memory cell array or reads data from the memory cell array. The test mode register set stores a delay value. In response to detecting a clock select signal received from outside the memory device, the test circuit generates an asynchronous signal from a clock received from the outside based on the delay value, and controls the peripheral circuit based on the asynchronous signal.

Memory device with test circuit which generates asychronous signal based on delay and controls peripheral circuit based on asynchronous signal, operating method of memory device, and operating method of test system including memory device

A test apparatus includes a device under test (DUT) configured to exchange data using a serial interface protocol and a test controller configured to receive a binary vector corresponding to a physical layer of the serial interface protocol from an external device and to buffer and transmit the received binary vector to the DUT.

Growing community of inventors

Asan-si, South Korea

Joosung Yun