Samsung Electronics Co., Ltd.

Joonyong Kim

Jongseob Kim

Junhyuk Park

Sunkyu Hwang

Jaejoon Oh

Injun Hwang

Younghwan Park

Soogine Chong

Dongchul Shin

Boram Kim

Woochul Jeon

Minchul Yu

Provided are a power device and a method of manufacturing the same. The power device may include a channel layer; a source and a drain at respective sides of the channel layer; a gate on the channel layer between the source and the drain; a passivation layer covering the source, the drain, and the gate; and a plurality of field plates in the passivation layer. The plurality of field plates may have different thicknesses. The plurality of field plates may have different widths, different pattern shapes, or both different widths and different pattern shapes.

Power device and method of manufacturing the same

Provided are a nitride semiconductor buffer structure and a semiconductor device including the same. The buffer structure may include a plurality of buffer layers between a substrate and an active layer. The active layer may include a nitride semiconductor. The plurality of buffer layers may be stacked on each other on the substrate. Each of the plurality of buffer layers may have a super lattice structure and may include a doped nitride semiconductor. The plurality of buffer layers may have different compositions from each other. Adjacent buffer layers, among the plurality of buffer layers, may have different doping concentrations from each other.

Nitride semiconductor buffer structure and semiconductor device including the same

The present disclosure provides a high electron mobility transistor including a channel layer; a barrier layer on the channel layer and configured to induce formation of a 2-dimensional electron gas (2DEG) to the channel layer; a p-type semiconductor layer on the barrier layer; a first passivation layer on the barrier layer and including a quaternary material of Al, Ga, O, and N; a gate electrode on the p-type semiconductor layer; and a source electrode and a drain electrode provided on both sides of the barrier layer and separated from the gate electrode.

High electron mobility transistor and method of manufacturing the same

A semiconductor integrated circuit device includes: a channel layer, a barrier layer; a first p-type semiconductor layer and a second p-type semiconductor layer, spaced apart from each other on the barrier layer; and a passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer. The passivation layer may partially inactivate a dopant of at least one of the first p-type semiconductor layer and the second p-type semiconductor layer.

Semiconductor IC device including passivation layer for inactivating a dopant in a p-type semiconductor layer and method of manufacturing the same

Provided is a high electron mobility transistor including: a channel layer comprising a 2-dimensional electron gas (2DEG); a barrier layer on the channel layer and comprising first regions and a second region, the first regions configured to induce the 2DEG of a first density in portions of the channel layer and the second region configured to induce the 2DEG of a second density different from the first density in other portions of the channel layer; source and drain electrodes on the barrier layer; a depletion formation layer formed on the barrier layer between the source and drain electrodes to form a depletion region in the 2DEG; and a gate electrode on the barrier layer. The first regions may include a first edge region and a second edge region corresponding to both ends of a surface of the gate electrode facing the channel layer.

Provided is a field effect transistor (FET) including a gradually varying composition channel. The FET includes: a drain region; a drift region on the drain region; a channel region on the drift region; a source region on the channel region; a gate penetrating the channel region and the source region in a vertical direction; and a gate oxide surrounding the gate. The channel region has a gradually varying composition along the vertical direction such that an intensity of a polarization in the channel region gradually varies.

Field effect transistor including gradually varying composition channel

A semiconductor device includes a channel layer including a channel; a channel supply layer on the channel layer; a channel separation pattern on the channel supply layer; a gate electrode pattern on the channel separation pattern; and an electric-field relaxation pattern protruding from a first lateral surface of the gate electrode pattern in a first direction parallel with an upper surface of the channel layer. An interface between the channel layer and the channel supply layer is adjacent to channel. A size of the gate electrode pattern in the first direction is different from a size of the channel separation pattern in the first direction. The gate electrode pattern and the electric-field relaxation pattern form a single structure.

Semiconductor device and method of fabricating the same

A high electron mobility transistor (HEMT) includes a channel layer comprising a group III-V compound semiconductor; a barrier layer comprising the group III-V compound semiconductor on the channel layer; a gate electrode on the barrier layer; a source electrode over gate electrode; a drain electrode spaced apart from the source electrode; and a metal wiring layer. A same layer of the metal wiring layer includes a gate wiring connected to the gate electrode, a source field plate connected to the source electrode, and a drain field plate connected to the drain electrode.

High electron mobility transistor

A high electron mobility transistor (HEMT) includes a channel layer, a plurality of barrier layers, and a p-type semiconductor layer. The barrier layers have an energy band gap greater than that of the channel layer. A gate electrode is arranged on the p-type semiconductor layer. A source electrode and a drain electrode are apart from the p-type semiconductor layer and the gate electrode on the barrier layers. Impurity concentrations of the barrier layers are different from each other in a drift area between the source electrode and the drain electrode.

A semiconductor thin film structure may include a substrate, a buffer layer on the substrate, and a semiconductor layer on the buffer layer, such that the buffer layer is between the semiconductor layer and the substrate. The buffer layer may include a plurality of unit layers. Each unit layer of the plurality of unit layers may include a first layer having first bandgap energy and a first thickness, a second layer having second bandgap energy and a second thickness, and a third layer having third bandgap energy and a third thickness. One layer having a lowest bandgap energy of the first, second, and third layers of the unit layer may be between another two layers of the first, second, and third layers of the unit layer.

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Seoul, South Korea

Joonyong Kim