Samsung Electronics Co., Ltd.

Joonsung Lim

Jaeho Ahn

Sukkang Sung

Jiwon Kim

Sungmin Hwang

Junhyoung Kim

Seungmin Lee

Woosung Yang

Bumkyu Kang

Kangmin Kim

Yonghoon Son

Junyeong Seok

Younggul Song

Byungjin Lee

Byungchul Jang

Jiyoung Kim

Eun Chu Oh

Eunchu Oh

Sangbeom Han

A semiconductor device includes a contact plug forming a signal path electrically connecting a bitline or wordlines and an upper connection pattern to each other, a lower insulating structure includes first and second insulating portions; the contact plug penetrates through the second insulating portion and contacts the upper connection pattern; the first insulating portion includes first and second lower layers, the second lower layer having a thickness smaller than the first lower layer; the second insulating portion includes a first upper layer contacting the second lower layer and covering a portion of an upper surface of the upper connection pattern, and a second upper layer on the first upper layer, the second upper layer having a thickness greater than the first upper layer; and materials of the second lower layer and first upper layer is different from materials of the first lower layer and the second upper layer.

Semiconductor device and data storage system including the same

A semiconductor device including a cell area including a first substrate, gate electrodes on the first substrate, a channel structure extending through the gate electrodes, cell contact plugs, a through contact plug, and first bonding pads, the first peripheral circuit area including second bonding pads on the first bonding pads; a second peripheral circuit area connected to the first peripheral circuit area; and a second substrate between the first peripheral circuit area and the second peripheral circuit area, the second substrate including a first surface in the first peripheral circuit area and a second surface in the second peripheral circuit area, wherein the second peripheral circuit area includes a device on the second surface, and a through electrode extending vertically through the second substrate and connected to the first peripheral circuit area.

Semiconductor device having peripheral circuit areas at both sides of substrate and data storage system including the same

A semiconductor device may include: a semiconductor substrate; a peripheral circuit structure on the semiconductor substrate; a plate pattern on the peripheral circuit structure and having a gap; and a stack structure on the plate pattern and including a first stack region and a second stack region. The first stack region may include gate electrodes stacked in a vertical direction perpendicular to an upper surface of the semiconductor substrate, and the second stack region may include both a conductor stack region including conductive layers stacked in the vertical direction and an insulator stack region including molded insulating layers at substantially the same height level as the conductive layers. The semiconductor device may also include vertical memory structure that extends through the first stack region; and source contact plugs electrically connected to at least one of the conductive layers of the conductor stack region and contacting the plate pattern.

Semiconductor devices and data storage systems including the same

A semiconductor device includes a stack structure including a gate stack region and dummy stack region. The gate stack region includes interlayer insulating layers and gate electrodes alternately stacked. The dummy stack region includes dummy insulating layers and dummy horizontal layers alternately stacked. A separation structure penetrates the stack structure. A vertical memory structure penetrates the gate stack region in a first region. A plurality of gate contact structures electrically connect to the gate electrodes in a second region. The gate electrodes include a first gate electrode and a second gate electrode disposed on a level higher than the first gate electrode. Each of the gate contact structures includes a gate contact plug and a first insulating spacer. The gate contact plugs include a first gate contact plug penetrating the second gate electrode and contacting the first gate electrode, and a second gate contact plug contacting the second gate electrode.

A semiconductor device and a data storage system including the same, the semiconductor device including: a first structure including a peripheral circuit; and a second structure, including: a pattern structure; an upper insulating layer; a stack structure between the first structure and the pattern structure and including first and second stack portions spaced apart from each other, the first and second stack portions respectively including horizontal conductive layers and interlayer insulating layers alternately stacked; separation structures penetrating through the stack structure; memory vertical structures penetrating through the first stack portion; and a contact structure penetrating through the second stack portion, the pattern structure, and the upper insulating layer, wherein the contact structure includes a lower contact plug penetrating through at least the second stack portion and an upper contact plug contacting the lower contact plug and extending upwardly to penetrate through the pattern structure and the upper insulating layer.

A semiconductor device includes a substrate having a first region and a second region, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, and extending by different lengths in a second direction on the second region to have pad regions in which upper surfaces thereof are exposed, channel structures penetrating the gate electrodes, extending in the first direction, and respectively including a channel layer, on the first region, contact plugs penetrating the pad regions of the gate electrodes and extending in the first direction, and contact insulating layers surrounding the contact plugs. The gate electrodes have side surfaces protruding further toward the contact plugs in the pad regions than ones of the gate electrodes therebelow.

A semiconductor device includes a first structure including a peripheral circuit and a second structure on the first structure. The second structure includes: a stack structure including first and second stack structures; separation structures passing through the first stack structure; a memory vertical structure between the separation structures and passing through the first stack structure; and a capacitor including first and second capacitor electrodes passing through the second stack structure and extending parallel to each other. The first stack structure includes spaced apart gate electrodes and interlayer insulating layers alternately stacked therewith. The second stack structure includes spaced apart first insulating layers, and second insulating layers alternately stacked therewith. Each of the first and second capacitor electrodes has a linear shape. The first and second insulating layers include a different material from each other. The second insulating layers include the same material as the interlayer insulating layers.

Semiconductor devices including capacitor electrodes

A semiconductor memory device includes: a semiconductor substrate having a first surface and a second surface opposing each other; a back-side insulating layer below the second surface of the semiconductor substrate; an external input/output conductive pattern below the back-side insulating layer; a circuit device including a gate electrode and a source/drain region, on the first surface of the semiconductor substrate; an internal input/output conductive pattern on the first surface of the semiconductor substrate, the internal input/output conductive pattern having at least a portion disposed on the same level as at least a portion of the gate electrode; a through-electrode structure penetrating through the semiconductor substrate and the back-side insulating layer and electrically connected to the internal input/output conductive pattern and the external input/output conductive pattern; and a memory cell array region disposed on a level higher than the circuit device, on the first surface of the semiconductor substrate.

A semiconductor device includes a substrate having a cell region and a connection region, a first stack structure with a plurality of first gate layers and a plurality of first interlayer insulating layers, and a second stack structure with a plurality of second gate layers and a plurality of second interlayer insulating layers. Each of the first gate layers includes a central portion in the cell region of the substrate and an end portion in the connection region of the substrate. Each of the second gate layers includes a central portion in the cell region of the substrate and an end portion in the connection region of the substrate. A thickness difference between the end and central portions of each first gate layer is different from a thickness difference between the end and central portions of each second gate layer.

Semiconductor device and electronic system including the same

A nonvolatile memory device and a data storage system including the same are provided. The nonvolatile memory device includes: a first structure including at least one first memory plane; and a second structure bonded to the first structure and including at least one second memory plane, wherein the number of the at least one first memory plane included in the first structure is different from the number of the at least one second memory plane included in the second structure.

Nonvolatile memory devices and data storage systems including the same

In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.

Method of operating nonvolatile memory device, nonvolatile memory device and memory controller performing the same

A memory device including a first structure; and a second structure on the first structure, wherein the first structure includes a first substrate; a peripheral circuit on the first substrate; a first insulating layer covering the first substrate and the peripheral circuit; and a first bonding pad on the first insulating layer, the second structure includes a second substrate; a memory cell array on a first surface of the second substrate; a second insulating layer covering the first surface of the second substrate and the memory cell array; a conductive pattern at least partially recessed from a second surface of the second substrate; and a second bonding pad on the second insulating layer, the first bonding pad is in contact with the second bonding pad, and the conductive pattern is spaced apart from the second insulating layer.

Memory device and data storage system including the same

A semiconductor device includes a first peripheral circuit region comprising a plurality of lower circuitries, a second peripheral circuit region apart from the first peripheral circuit region in a vertical direction, the second peripheral circuit region comprising a plurality of upper circuitries, and a cell region comprising a plurality of word lines, the cell region between the first peripheral circuit region and the second peripheral circuit region in the vertical direction. The plurality of word lines comprise a first word line connected to a first lower circuitry selected from the plurality of lower circuitries and a second word line connected to a first upper circuitry selected from the plurality of upper circuitries.

Semiconductor device and electronic system

A three-dimensional (3D) storage device using wafer-to-wafer bonding is disclosed. In the storage device, a first chip including a peripheral circuit region including a first control logic circuit configured to control operation modes of a nonvolatile memory (NVM) device is wafer-bonded with a second chip including 3D arrays of NVM cells, and a memory controller includes a third chip including a control circuit region. The control circuit region of the third chip includes a second control logic circuit associated with operation conditions of the NVM device, and the second control logic circuit includes a serializer/deserializer (SERDES) interface configured to share random access memory (RAM) in the memory controller and transmit and receive data to and from the NVM device.

Growing community of inventors

SEONGNAM-SI, South Korea

Joonsung Lim