Samsung Electronics Co., Ltd.

Kolon Life Science, Inc.

Joonsung Kim

Doohwan Lee

Yangsoo Kwon

Yongin Choi

Jinwoo Oh

Jaehoon Choi

Bongsoo Kim

Eunseok Cho

Taeho Ko

Jinseon Park

Khaile Kim

Seokbong Park

Jangjoon Park

Jongho Cho

Yeomoon Sim

Yejin Kwon

Sujeong Kim

Minjung Kim

Soondong Lee

Jong-Min Lee

Jaeho Kim

Jiwon Kim

Hyesun Lee

Yonghwan Kwon

Mingoo Kim

Sukkang Sung

Euntaek Jung

Sanguk Kim

SeokWon Lee

Daewook Kim

Minju Kim

Youngseok Jung

Inhyoung Kim

Jinwon Choi

Heonsik Choi

Sangdon Lee

Hwanjun Choi

Minjeong Gu

Jieun Hong

Jaeil Shin

Eunjin Lee

Haesu Kang

Soonoh Hong

A semiconductor device includes an electrode structure including electrodes stacked on a substrate and an insulating pattern on an uppermost electrode of the electrodes, a vertical structure that penetrates the electrode structure and is connected to the substrate, a first insulating layer on the electrode and the vertical structure, a conductive pattern that penetrates the first insulating layer and is connected to the vertical structure, an upper horizontal electrode on the conductive pattern, and an upper semiconductor pattern that penetrates the upper horizontal electrode and is connected to the conductive pattern. The conductive pattern has a first side surface on the vertical structure and a second side surface on the insulating pattern.

Semiconductor device including separate upper channel structures and electronic system including the same

A semiconductor package includes a connection substrate on a package substrate and has an opening that penetrates therethrough. A chip stack is on the package substrate and in the opening. A redistribution layer is on the connection substrate and the chip stack. An upper semiconductor chip is on first redistribution pads of the redistribution layer. External terminals are on a bottom surface of the package substrate. The chip stack includes a first semiconductor chip on substrate pads of the package substrate, and a second semiconductor chip on the first semiconductor chip and second redistribution pads of the redistribution layer. The redistribution layer includes a first region that overlaps the upper semiconductor chip and a second region beside the upper semiconductor chip. The first redistribution pads are on the first region. The second redistribution pads are on the second region.

Semiconductor package

An apparatus and a method for effectively mapping a reference signal for vehicle-to-everything (V2X) communication in a wireless communication system are provided. A transmission terminal performing the V2X communication includes a processor generating sidelink control information (SCI) and a transceiver transmitting the generated SCI to a reception terminal through a physical sidelink control channel (PSCCH) and a physical sidelink shared channel (PSSCH). A decision on whether to allocate a demodulation reference signal (DMRS) of the PSSCH and the PSCCH to the same orthogonal frequency division multiplexing (OFDM) symbol is made based on a number of subchannels and at least one sized thereof.

Apparatus and method for effectively mapping reference signal for V2X communication in wireless communication system

A fan-out semiconductor package includes: a package body including a fan-in area corresponding to a through-hole located therein, a fan-out area surrounding the fan-in area, and a body interconnect structure arranged in the package body corresponding to the fan-out area; a fan-in chip structure located in the through-hole, the fan-in chip structure comprising a first chip, a capacitor chip arranged to be apart from the first chip, and a second chip disposed on both the first chip and the capacitor chip; a redistribution structure arranged on a bottom surface of the package body and a bottom surface of the fan-in chip structure and including a redistribution element extending to the fan-out area; and an interconnect via arranged on a top surface of the package body and electrically connected to the redistribution element in the fan-out area.

Fan-out semiconductor package

A method of manufacturing a semiconductor package is provided and includes: forming a lower redistribution structure, the lower redistribution structure including lower redistribution patterns having lower connection pads; forming an upper redistribution structure on a boundary surface of the lower redistribution structure, the upper redistribution structure including upper redistribution patterns having upper connection pads electrically connected to the lower connection pads; forming openings exposing at least a portion of each of the lower connection pads; disposing an interposer substrate, including the lower redistribution structure and the upper redistribution structure, on a base substrate, the lower connection pads of the interposer substrate electrically connected to wiring patterns of the base substrate through lower connection bumps disposed on the openings; and disposing at least one of semiconductor chips, including connection pads, on the interposer substrate, the connection pads electrically connected to the upper connection pads through upper connection bumps.

A fan-out semiconductor package includes a frame substrate having a through hole therein, a semiconductor chip in the through hole, wherein the semiconductor chip includes a chip body, a chip pad on a surface of the chip body and a passivation layer on the chip body and on the chip pad, an encapsulation layer on side surfaces of the semiconductor chip within the through hole, and a guard ring on the passivation layer and on an edge portion of the chip body.

Fan-out semiconductor packages

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate and a first chip pad on a first bottom surface of the first semiconductor substrate, a second semiconductor chip including a second semiconductor substrate and a second chip pad on a second top surface of the second semiconductor substrate, a lower redistribution structure provided under the first semiconductor chip and the second semiconductor chip, the lower redistribution structure including a lower redistribution pattern, the lower redistribution pattern including a first lower redistribution via pattern contacting the first chip pad, a molding layer covering the first semiconductor chip and the second semiconductor chip, an upper redistribution structure including an upper redistribution pattern, the upper redistribution pattern including a first upper redistribution via pattern connected to the second chip pad, and a conductive connection structure electrically connecting the lower redistribution pattern to the upper redistribution pattern.

An operating method of a terminal configured to perform vehicle-to-everything (V2X) communication in a wireless communication system, including signaling a maximum physical sidelink feedback channel (PSFCH) receiving capability to a base station; and receiving a wireless signal transmitted from the base station based on the maximum PSFCH receiving capability, wherein the maximum PSFCH receiving capability is a maximum number of PSFCHs receivable during one time transmission interval (TTI).

Apparatus and method for efficiently transceiving PSFCH for V2X communication in wireless communication system

A semiconductor package is provided. The semiconductor package includes a chip pad of a semiconductor chip, the chip pad including a connection portion and a test portion in a first surface of the chip pad; a barrier layer covering the chip pad, the barrier layer defining a first opening and a second opening that is separate from the first opening, the first opening exposing the connection portion of the chip pad, and the second opening exposing the test portion of the chip pad; and a redistribution structure.

Semiconductor package including a chip pad having a connection portion and test portion in a first surface of the chip pad

A semiconductor package includes a base substrate including a wiring pattern, an interposer substrate including lower and upper redistribution patterns, a semiconductor structure, a heat dissipation structure, a plurality of external connection bumps disposed on a lower surface of the base substrate, a plurality of lower connection bumps disposed between the base substrate and the interposer substrate, and a plurality of upper connection bumps disposed between the interposer substrate and the semiconductor structure.

A method of manufacturing a fan-out semiconductor package includes forming a frame having a through-hole and including one or more wiring layers; forming a semiconductor chip in the through-hole of the frame; forming an encapsulant covering an upper surface of each of the frame and the semiconductor chip, and filling a space between a wall surface of the through-hole of the frame and a side surface of the semiconductor chip; forming a connection structure below each of the frame and the semiconductor chip; forming a first metal pattern layer on an upper surface of the encapsulant; forming an insulating material on the upper surface of the encapsulant and covering the first metal pattern layer; and forming a second metal pattern layer on the insulating material, a first metal via passing through the insulating material, and a second metal via passing through the insulating material and the encapsulant.

A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.

Semiconductor packages

An operating method of a communication device for providing a beamformed transmission signal to a plurality of terminals may include determining a target transmission vector based on an area restriction condition for each of the plurality of terminals, generating a beam selection matrix for selecting some of a plurality of antennas based on the target transmission vector and a beam selection condition, generating a precoding matrix based on the target transmission vector and the beam selection matrix, and generating a transmission signal based on the beam selection matrix and the precoding matrix.

Communication device for performing beamforming and operating method thereof

A method of receiving a downlink control channel in a user equipment may include receiving, using two or more antenna ports, a shortened physical downlink control channel (PDCCH) transmitted using a space-frequency block code (SFBC), by using at least one shortened control channel element (SCCE) for shortened transmission time interval (STTI) transmission; and monitoring the shortened PDCCH. The at least one SCCE may include at least one shortened resource element group (REG) including a number of resource elements (REs), where the number is unequal to an integer multiple of the number of antenna ports allocated to the shortened PDCCH.

Growing community of inventors

Suwon-si, South Korea

Joonsung Kim