Samsung Electronics Co., Ltd.

Joonhee Lee

Seong Soon Cho

Dongseog Eun

Sung-Hun Lee

Jintaek Park

Chang-Sup Lee

Byoungil Lee

Jiyoung Kim

Jongwon Kim

Kwangyoung Jung

Sejie Takaki

Young-Ho Lee

Seok-Won Lee

Sangwook Han

Yoocheol Shin

Euntaek Jung

Seonghun Jeong

Seong-hun Jeong

Bosuk Kang

Jaehyun Lim

Joon-Sung Lim

Jongwon Choi

Seul Gee Lee

Sung-Jun Lee

Thomas Byunghak Cho

Woosung Yang

Bonghyun Choi

Yujin Seo

Hojun Seong

Shinwoong Kim

Myounggyun Kim

Changdae Jung

A semiconductor device includes a peripheral circuit region with a first substrate, circuit devices on the first substrate, and a first wiring structure, a memory cell region with a second substrate that has a first region and a second region, gate electrodes stacked in the first region, channel structures that penetrate the gate electrodes, a first horizontal conductive layer on the second substrate in the first region, an insulating region on the second substrate in the second region, a second horizontal conductive layer on the first horizontal conductive layer and the insulating region, and a second wiring structure, and a third wiring structure that connects the first substrate to the second substrate, and includes an upper via that penetrates the second horizontal conductive layer, the insulating region, and the second substrate, and a lower wiring structure connected to the upper.

Semiconductor device

A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

Three-dimensional semiconductor memory device with increased process margin

A semiconductor device includes a substrate having a first region and a second region, gate electrodes spaced apart from each other in a first direction, perpendicular to an upper surface of the substrate, and extend in a second direction, and have different lengths on the second region, channel structures that penetrate the gate electrodes, extend in the first direction, and respectively include a channel layer on the first region, support structures that penetrate the gate electrodes and extend in the first direction on the second region, and a separation region that penetrates the gate electrodes and extend in the second direction. The substrate has a recess region that overlaps the separation region in the first direction and extends downward from an upper surface in the second region, adjacent to the first region. The separation region has a protrusion that protrudes downward to correspond to the recess region.

Semiconductor device and data storage system including the same

A semiconductor device includes a substrate including a lower horizontal layer and an upper horizontal layer and having a cell array region and a connection region, an electrode structure including electrodes, which are stacked above the substrate, and which extend from the cell array region to the connection region, a vertical channel structure on the cell array region that penetrates the electrode structure and is connected to the substrate, and a separation structure on the connection region that penetrates the electrode structure. The lower horizontal layer has a first top surface in contact with a first portion of the separation structure, and a second top surface in contact with a second portion of the separation structure, and an inflection point at which a height of the lower horizontal layer is abruptly changed between the first top surface and the second top surface.

Three-dimensional semiconductor memory devices

A semiconductor device includes a peripheral circuit structure including a first substrate and circuit elements on the first substrate; and a memory cell structure including a second substrate on the first substrate, a first horizontal conductive layer on the second substrate, a second horizontal conductive layer on the first horizontal conductive layer, gate electrodes spaced apart from each other and stacked on the second horizontal conductive layer, channel structures penetrating through the gate electrodes, and separation regions penetrating the gate electrodes, extending, and spaced apart from each other. The semiconductor device has a through-wiring region including a through-contact plug electrically connecting the memory cell structure and the peripheral circuit structure, the separation regions include first separation regions adjacent to the through-contact plug, and the first separation regions penetrate through the second horizontal conductive layer and are spaced apart from the first horizontal conductive layer.

Semiconductor devices and data storage systems including the same

A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure. The second portion of the intermediate pattern layer has a side surface that is lowered while forming a surface curved from an upper surface of the first portion and that contacts the upper pattern layer.

Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

Three-dimensional semiconductor memory device and method of fabricating the same

Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.

Semiconductor devices

Three-dimensional semiconductor memory device including an electrode connecting portion

An electronic device includes a phase locked loop configured to perform a two-point modulation operation on a data signal by using first and second modulation paths, and the phase locked loop is configured to generate, based on a differential value of a first phase error signal generated in the first modulation path, a gain for adjusting a frequency variation of the data signal through the second modulation path so as to match with the frequency variation of the data signal through the first modulation path.

Phase locked loop and electronic device including the same

Semiconductor devices are provided. A semiconductor device includes a stack of alternating gates and insulating layers. The semiconductor device includes a dummy cell region. The semiconductor device includes a plurality of bit lines and a plurality of auxiliary bit lines. Some of the plurality of auxiliary bit lines have different respective lengths. Related methods of forming semiconductor devices are also provided.

Semiconductor devices including auxiliary bit lines

Growing community of inventors

Seongnam-si, South Korea

Joonhee Lee