Samsung Electronics Co., Ltd.

Joongchan Shin

Sangyeon Han

Taehyun An

Hyungeun Choi

Kiseok Lee

Hui-Jung Kim

Eunju Cho

Yoosang Hwang

Jiyoung Kim

Dongsuk Shin

Sung-Min Park

Moonyoung Jeong

Seungjae Jung

Hokyun An

Chan Min Lee

Seokho Shin

Changkyu Kim

Iljae Shin

Ahram Lee

Byeungmoo Kang

Taegyu Kang

A three-dimensional (3D) semiconductor memory device including: stack structures spaced apart from each other on a semiconductor substrate, wherein each of the stack structures includes interlayer insulating layers and semiconductor patterns alternately stacked on the semiconductor substrate; conductive patterns provided between the interlayer insulating layers vertically adjacent to each other and connected to the semiconductor patterns; and a protective structure covering a top surface of the semiconductor substrate between the stack structures, wherein a top surface of the protective structure is located between a top surface and a bottom surface of a lowermost interlayer insulating layer of the interlayer insulating layers.

Three-dimensional semiconductor memory device and a method of manufacturing the same

A semiconductor memory device includes: a bit line extending on a substrate in a vertical direction; a transistor body part including a first source-drain region, a monocrystalline channel layer, and a second source-drain region that are sequentially arranged in a first horizontal direction and connected to the bit line; gate electrode layers extending in a second horizontal direction that is orthogonal to the first horizontal direction, with a gate dielectric layer between the gate electrode layers and the monocrystalline channel layer, and covering upper and lower surfaces of the monocrystalline channel layer; and a cell capacitor including a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer at a side of the transistor body that is opposite to the bit line in the first horizontal direction and is connected to the second source-drain region.

Semiconductor memory device

A semiconductor memory device including a substrate; a semiconductor pattern extending in a first horizontal direction on the substrate; bit lines extending in a second horizontal direction on the substrate perpendicular to the first horizontal direction, the bit lines being at a first end of the semiconductor pattern; word lines extending in a vertical direction on the substrate at a side of the semiconductor pattern; a capacitor structure on a second end of the semiconductor pattern opposite to the first end in the first horizontal direction, the capacitor structure including a lower electrode connected to the semiconductor pattern, an upper electrode spaced apart from the lower electrode, and a capacitor dielectric layer between the lower electrode and the upper electrode; and a capacitor contact layer between the second end of the semiconductor pattern and the lower electrode and including a pair of convex surfaces in contact with the semiconductor pattern.

Semiconductor memory devices

A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.

Three-dimensional semiconductor memory device

A semiconductor memory device includes a substrate having a cell region and a contact region with a peripheral circuit region, first and second stacks on the cell region, and a first peripheral transistor on the peripheral circuit region. Each of the first and second stacks includes semiconductor patterns stacked, in a vertical direction, on the cell region, bit lines stacked in the vertical direction on the cell region and respectively connected to first ends of the semiconductor patterns, each of the bit lines extending, in a horizontal direction with respect to the upper surface of the substrate, from the cell region to the contact region, and a word line disposed adjacent to the semiconductor patterns and extending in the vertical direction from the cell region of the substrate. The first peripheral transistor is disposed between the bit lines of the first stack and the bit lines of the second stack.

Disclosed is a semiconductor memory device including a stack structure including layers which are vertically stacked on a substrate and each of which includes a bit line extending in a first direction and a semiconductor pattern extending in a second direction from the bit line, a gate electrode which is in a hole penetrating the stack structure and extending along a stack of semiconductor patterns, a vertical insulating layer covering the gate electrode and filling the hole, and a data storage element electrically connected to the semiconductor pattern. The data storage element includes a first electrode, which is in a first recess of the vertical insulating layer and has a cylindrical shape whose one end is opened, and a second electrode, which includes a first protrusion in a cylinder of the first electrode and a second protrusion in a second recess of the vertical insulating layer.

Growing community of inventors

Seoul, South Korea

Joongchan Shin