Samsung Electronics Co., Ltd.

Joong-won Jeon

Hyun-Jo Kim

Suk-Joo Lee

Jong-Doo Kim

Hee-Sung Kang

Dal-Hee Lee

Seong-Yul Park

Ji-Youn Song

Jeong-Lim Kim

Mun-Su Shin

Dae-Ho Yoon

Young-Deok Kwon

Provided is an integrated circuit (IC) device including a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first device region and the second device region are arranged apart from each other in a first direction that is perpendicular to a second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.

Integrated circuit (IC) device

Methods of inspecting photomasks are provided. A method of inspecting a photomask includes electronically inspecting a first mask pattern in a mask region of the photomask and refraining from electronically inspecting a separate second mask pattern in the mask region of the photomask. The first mask pattern includes a geometric feature that corresponds to at least a portion of the second mask pattern. Moreover, the mask region is outside of a scribe lane region of the photomask. Related methods of manufacturing photomasks and methods of manufacturing semiconductor devices are also provided.

Methods of manufacturing photomasks, methods of inspecting photomasks, and methods of manufacturing semiconductor devices

A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes forming an interlayer insulating layer that comprises a first region and a second region, forming an etch stop pattern for exposing the second region in the first region of the interlayer insulating layer and forming a mask pattern that comprises a first via-hole that exposes an upper surface of the etch stop pattern and a second via-hole that penetrates the interlayer insulating layer on the interlayer insulating layer and the etch stop pattern.

Method for fabricating semiconductor device including a via hole in a mask pattern

A method of designing patterns of semiconductor devices includes forming a plurality of tiles having patterns on a wafer, measuring the patterns of the plurality of tiles, analyzing the measurements of the patterns and determining a tile having such a size that the measurements linearly vary according to a design size and pattern density, and modifying the pattern density of the determined tile.

Method of designing patterns of semiconductor devices in consideration of pattern density

A semiconductor device includes a logic region disposed in a central region of the semiconductor device, and a peripheral region disposed in an outer region thereof. The logic region includes a line-shaped logic transistor and a box-shaped decoupling capacitor. The peripheral region includes a line-shaped peripheral transistor and a line-shaped peripheral dummy transistor disposed adjacent to the peripheral transistor.

Growing community of inventors

Seoul, South Korea

Joong-won Jeon