Samsung Electronics Co., Ltd.

Joong Shik Shin

Hyun Mog Park

Seung Jun Shin

Kang Min Kim

Byoung Il Lee

Geun Won Lim

Jin Hyuk Kim

Jung Tae Sung

Sang Jun Hong

Sung Hyung Lee

Ee Jou Kim

Ji Hoon Park

Seung Min Song

Yong Jin Kwon

Dong Seog Eun

Jun Ho Cha

Kyung Jun Shin

Hyun Kook Lee

Eun Taek Jung

Jong Ho Woo

Beyoung Hyun Koh

A semiconductor memory device may include a mold structure that includes mold insulation films and gate electrodes alternately stacked on a first substrate, a channel structure that penetrates the mold structure and intersects the gate electrodes, a block separation region that extends in a first direction parallel to an upper surface of the first substrate and cuts the mold structure, a first dam region and a second dam region spaced apart from each other, that each having a closed loop in a plan view and each cutting the mold structure, pad insulation films in the first and second dam regions that are alternately stacked with the mold insulation films and include a material different from the mold insulation films, and a through via which penetrates through the first substrate, the mold insulation films, and the pad insulation films, in the first dam region but not in the second dam region.

Semiconductor memory devices, methods for fabricating the same and electronic systems including the same

A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.

Semiconductor device

A semiconductor device includes a first substrate including a cell region and surrounded by an extension region, a common source plate on the first substrate, a supporter on the common source plate, a first stack structure on the supporter and including an alternately stacked first insulating film and first gate electrode, a channel hole penetrating the first stack structure, the supporter, and the common source plate on the cell region, and an electrode isolation trench spaced apart from the channel hole in a first direction on the cell region, extending in a second direction, and penetrating the first stack structure, the supporter, and the common source plate, wherein a first thickness of the supporter in a first region adjacent to the electrode isolation trench is greater than a second thickness of the supporter in a second region formed between the electrode isolation trench and the channel hole.

A nonvolatile memory device with improved product reliability and a method of fabricating the same is provided. The nonvolatile memory device comprises a substrate, a first mold structure disposed on the substrate and including a plurality of first gate electrodes, a second mold structure disposed on the first mold structure and including a plurality of second gate electrodes and a plurality of channel structures intersecting the first gate electrodes and the second gate electrodes by penetrating the first and second mold structures, wherein the first mold structure includes first and second stacks, which are spaced apart from each other, and the second mold structure includes a third stack, which is stacked on the first stack, a fourth stack, which is stacked on the second stack, and first connecting parts, which connect the third and fourth stacks.

Nonvolatile memory device with h-shaped blocks and method of fabricating the same

A semiconductor device comprises a lower conductive layer on a substrate. A conductive line is on the lower conductive layer. A buried trench in the conductive line is provided. A supporter which is on the conductive line and extends in the buried trench is provided. A stack structure including a plurality of insulating layers and a plurality of conductive layers that are alternately stacked is on the supporter. A channel structure passing through the stack structure, the supporter, and the conductive line is provided. An isolation trench passing through the stack structure, the supporter, and the conductive line is provided.

3D semiconductor devices including a supporter and methods of forming the same

A semiconductor device includes a substrate having a first region and a second region, the first region including memory cells, and the second region including transistors for driving the memory cells, and device isolation regions disposed within the substrate to define active regions of the substrate. The active regions include a first guard active region surrounding the first region, a second guard active region surrounding a portion of the second region, and at least one dummy active region disposed between the first guard active region and the second guard active region.

A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.

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Yongin-si, South Korea

Joong Shik Shin