Advanced Micro Devices Corporation

Spansion Llc.

Globalfoundries Inc.

Advnaced Micro Devices, Inc.

Joong Jeon

Huicai Zhong

Arvind Halliyal

Minh Van Ngo

Qi Xiang

Robert B Ogle

Hidehiko Shiraiwa

George Jonathan Kluth

William George En

Effiong Etukudo Ibok

Takashi Whitney Orimoto

Ming-Ren Lin

Wei Zheng

Meng Ding

Jung-Suk Goo

Rinji Sugino

Hyeon-Seag Kim

Allison Holbrook

Harpreet Kaur Sachar

Robert B Clark-Phelps

Bhanwar Singh

Mark T Ramsbey

Matthew S Buynoski

Calvin T Gabriel

Shenqing Fang

Haihong Wang

Mark W Randolph

Jeffrey Allan Shields

Cyrus E Tabery

Eric N Paton

Simon S Chan

Chih-Yuh Yang

Bryan K Choo

Lei Xue

Youseok Suh

Wenmei Li

Kuo Tung Chang

Jaeyong Park

Satoshi Torii

Wen Yu

Ercan Adem

Weidong Qian

Robert J Chiu

Fred Cheung

David H Matsumoto

Austin Frenkel

Robert Bertram Ogle, Jr

Winny Stockwell

Colman Wong

A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.

Memory cell system with multiple nitride layers

A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a third dielectric layer formed over the second dielectric layer. The third dielectric layer may have a high dielectric constant and may be deposited at a relatively high temperature. A control gate may be formed over the third dielectric layer.

Non-volatile memory device with improved erase speed

A system and method are disclosed for processing a zero angstrom oxide interface dual poly gate structure for a flash memory device. An exemplary method can include removing an oxide on a surface of a first poly layer and forming a second poly layer on the first poly layer in a same processing chamber. A transfer of the structure is not needed from an oxide removal tool to, for example, a poly layer formation tool, an implant tool, and the like. As a result, impurities containing a silicon oxide caused by exposure of the first poly layer to an oxygen-containing atmosphere do not form at the interface of the first and second poly layers.

Zero interface polysilicon to polysilicon gate for flash memory

In fabricating an electronic structure, a substrate is provided, and a first barrier layer is provided on the substrate. A germanium thin film diode is provided on the first barrier layer, and a second barrier layer is provided on the germanium thin film diode. A memory device is provided over and connected to the second barrier layer.

Thin film germanium diode with low reverse breakdown

A semiconductor memory device may include an intergate dielectric layer of a high-K dielectric material interposed between a floating gate and a control gate. With this intergate high-K dielectric in place, the memory device may be erased using Fowler-Nordheim tunneling.

SONOS memory cell having high-K dielectric

A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory device may be efficiently erased using Fowler-Nordheim tunneling.

Memory cell having enhanced high-K dielectric

A semiconductor memory device may include an intergate dielectric layer of high-K dielectric materials interposed between a charge storing layer and a control gate. The high-K materials may be deposited in such a manner that the materials are gradually graded with respect to one another.

SONOS memory cell having a graded high-K dielectric

Methods are disclosed for fabricating multi-bit SONOS flash memory cells, comprising forming a first dielectric layer and a charge trapping layer over a substrate of a wafer and selectively etching the dielectric and charge trapping layers down to a substrate region to form a bitline opening, then implanting a dopant ion species into the substrate associated with the bitline opening in a bitline region. A radical oxidation process is then used to form a second dielectric layer of a triple layer dielectric-charge trapping-dielectric stack over the charge trapping layer and to fill the bitline opening in the bitline regions of the wafer. Finally, a wordline structure is then formed over the triple layer dielectric-charge trapping-dielectric stack and the bitline regions of the wafer. A multi-bit flash memory array is also disclosed, comprising a bitline region in a substrate, a first dielectric layer overlying the substrate substantially adjacent to and substantially exposing the bitline region, a charge trapping layer overlying the first dielectric layer substantially adjacent to and substantially exposing the bitline region, a bitline oxide isolation structure or layer extending continuously over the bitline region and charge trapping layer, the isolation structure comprising a single dielectric material layer formed by the radical oxidation process, and a conductive wordline overlying the bitline oxide isolation structure or layer.

Radical oxidation for bitline oxide of SONOS

For fabricating a memory device, spacers are formed to sides of word-line gates. In addition, aluminum oxide is formed as one of a liner layer or a cover layer to the spacers. The aluminum oxide has a chemical composition of AlOfor example. Such aluminum oxide may be used as an etch stop layer in a periphery region, a metal silicide block, and a hydrogen block for enhanced performance of the memory device.

Aluminum oxide as liner or cover layer to spacers in memory device

According to one exemplary embodiment, a method for integrating first and second metal layers on a substrate to form a dual metal NMOS gate and PMOS gate comprises depositing a dielectric layer over an NMOS region and a PMOS region of the substrate. The method further comprises depositing the first metal layer over dielectric layer. The method further comprises depositing the second metal layer over the first metal layer. The method further comprises implanting nitrogen in the NMOS region of substrate and converting a first portion of the first metal layer into a metal oxide layer and converting a second portion of the first metal layer into metal nitride layer. The method further comprises forming the NMOS gate and the PMOS gate, where the NMOS gate comprises a segment of metal nitride layer and the PMOS gate comprises a segment of the metal oxide layer.

CMOS gates formed by integrating metals having different work functions and having a high-k gate dielectric

According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate comprises a step of forming a buffer layer on the substrate, where the buffer layer comprises ALD silicon dioxide. The buffer layer can be formed by utilizing a silicon tetrachloride precursor in an atomic layer deposition process, for example. The buffer layer comprises substantially no pin-hole defects and may have a thickness, for example, that is less than approximately 5.0 Angstroms. The method further comprises forming a high-k dielectric layer over the buffer layer. The high-k dielectric layer may be, for example, hafnium oxide, zirconium oxide, or aluminum oxide. According to this exemplary embodiment, the method further comprises forming a gate electrode layer over the high-k dielectric layer. The gate electrode layer may be polycrystalline silicon, for example.

Method for forming a thin, high quality buffer layer in a field effect transistor and related structure

A method for modulating the flatband voltage of semiconductor devices includes post-deposition annealing of a high-k dielectric film deposited by chemical vapor deposition, for example. The modulation of the flatband voltage, and thus, the threshold voltage of MOSFET devices, is achieved by post-deposition annealing of the high-k dielectric film and control of the annealing parameters. These include annealing gases, annealing temperatures and annealing times.

Method for modulating flatband voltage of devices having high-k gate dielectrics by post-deposition annealing

A semiconductor component having smooth, void-free conductive layers and a method for manufacturing the semiconductor component. Surface features such as gate structures are formed on a semiconductor substrate. A layer of insulating material is formed on the gate structures and a layer of polysilicon is formed on the layer of insulating material. The layer of polysilicon is annealed in a hydrogen ambient to redistribute the silicon atoms of the polysilicon layer. Redistribution of the atoms fills voids that may be present in the layer of polysilicon and smoothes the surface of the layer of polysilicon. Another layer of polysilicon is formed over the annealed layer of polysilicon. This polysilicon layer is annealed in a hydrogen ambient to redistribute the silicon atoms and smooth the surface of the polysilicon layer, thereby forming a subsequently annealed polysilicon layer. Control gate structures are formed from the subsequently annealed polysilicon layer.

Semiconductor component and method of manufacture

According to one embodiment, a memory cell structure comprises a semiconductor substrate, a first silicon oxide layer situated over the semiconductor substrate, a charge storing layer situated over the first silicon oxide layer, a second silicon oxide layer situated over the charge storing layer, and a gate layer situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer. The reduced charge loss in the charge storing layer has the benefit of reducing threshold voltage shifts, programming data loss, and programming capability loss in the memory device, thereby improving memory device performance.

Memory cell structure having nitride layer with reduced charge loss and method for fabricating same

According to one exemplary embodiment, a method for forming a field effect transistor over a substrate comprises a step of forming an interfacial oxide layer over a channel region of the substrate, where the interfacial oxide layer has a first thickness. The interfacial oxide layer can prevent a high-k element from diffusing into the channel region. The method further comprises forming an oxygen-attracting layer over the interfacial oxide layer, where the oxygen-attracting layer prevents the first thickness of the interfacial oxide layer from increasing. The oxygen-attracting layer is formed by forming a metal layer over the interfacial oxide layer, where the metal layer combines with oxygen to form a silicate. The oxygen-attracting layer may be zirconium silicate or hafnium silicate, for example. The method further comprises forming a high-k dielectric layer over the oxygen-attracting layer. The method further comprises forming a gate electrode layer over the high-k dielectric layer.

Method for forming a field effect transistor having a high-k gate dielectric

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Cupertino, CA, United States of America

Joong Jeon