Samsung Electronics Co., Ltd.

Hyundai Electronics Industries Co. Ltd.

University of Seoul Industry Cooperation Foundation

University of Seoul Foundation of Industry Academic Cooperation

Joong-ho Choi

Jai-kwang Shin

Ho-jung Kim

Hyun-sik Choi

Ki-chul Kim

Hyung-su Jeong

Jin-Hong Ahn

Boo Yong Park

A logic device may include a first functional block, the first functional block including, a first storage block, a second storage block, and a first function controller. In a first operation time period, the first function controller may be configured to receive a first configuration selection signal and a first configuration command signal that instructs a first function be configured, select the first storage block as a configured storage block in the first operation time period based on the first configuration selection signal, and configure the first function in the first storage block based on the first configuration command signal.

Logic device and method of operating the same

A multi-valued logic device having an improved reliability includes a conversion unit configured to convert a multi level signal into a plurality of partial signals; and a plurality of nonvolatile memory devices configured to individually store the plurality of partial signals, wherein a number of bits of each of the plurality of partial signals individually stored in the plurality of nonvolatile memory devices is less than the number of bits of the multi level signal.

Multi-valued logic device having nonvolatile memory device

A delay time compensation circuit for a clock buffer includes first and second toggle flip-flops multiplying an input clock signal and a delay clock signal which is delayed by an input buffer, respectively, a time interval extraction chain extracting a time interval between a rising edge of the input clock signal and a rising edge of the delay clock signal in accordance with clock signals multiplied in the first and second toggle flip-flops, and a variable delay chain delaying the input clock signal by a time interval extracted from the time interval extraction chain. The circuit employs a &frac12; multiplied clock signal and operates without regard to a duty cycle of an input clock signal, thereby compensating for all the delay time within the cycle of the input clock signal.

Delay time compensation circuit for clock buffer

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Seoul, South Korea

Joong-ho Choi