Skhynix Inc.

Joon Woo Choi

Chang Ki Baek

A semiconductor memory apparatus includes a plurality of memory cells. Each memory cell includes a switching element and a storage capacitor. The semiconductor memory apparatus further includes a first word line extended from a part of the plurality of memory cells, a second word line which is enabled after the first word line is enabled in a refresh mode for refreshing data stored in the storage capacitor, a word line control circuit configured to enable and disable the first word line. The word line control circuit comprises at least one switch that couples and decouples the first word line and the second word line.

Semiconductor memory apparatus operating in a refresh mode and method for performing the same

A semiconductor memory apparatus includes a word line control circuit configured to enable and disable a word line, wherein the word line control circuit comprises a switch which couples and decouples the word line to and from at least one other word line.

Semiconductor memory apparatus

A data input circuit of a semiconductor apparatus may include a plurality of parallelizing units corresponding to a plurality of input/output pads in a one-to-one manner, and a data control block configured to transmit serial test data, which may be input through less than all of the plurality of input/output pads, to the plurality of parallelizing units in response to first and second control signals.

Data input circuit of semiconductor apparatus

A semiconductor device includes a first input/output (I/O) part buffering command/address (C/A) signals inputted through a first pad part to generate delay address signals, an internal address generator generating a plurality of internal address signals according to a level combination of the delay address signals, and a second I/O part including a plurality of fuses selected by the plurality of internal address signals in a test mode. The plurality of fuses of the second I/O part are programmed according to logic levels of data inputted to the second I/O part through a second pad part to control I/O characteristics of the second I/O part.

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Icheon-si, South Korea

Joon Woo Choi