Samsung Electronics Co., Ltd.

Joon-wan Chai

Kwang-il Park

Seung-ju Kim

Tae-ho Lee

In Huh

Youn-sik Park

Hyo-jin Choi

Chang-wook Jeong

Jeong-hoon Ko

Jun-haeng Lee

Hyun-sun Park

Young-min Oh

Kye-hyun Kyung

A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Device for generating verification vector for circuit design verification, circuit design system, and reinforcement learning method of the device and the circuit design system

A device for verifying a circuit design including a first circuit block and a second circuit block includes a verification vector generator and a design verifier. The verification vector generator determines a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block. The design verifier performs design verification for the first circuit block by using the first verification vector.

An address buffer only having (N/2) stages, capable of performing the same function as that of an N-stage address buffer is provided. The address buffer used in a semiconductor device having N (where N is a natural number) additive latency comprises (N/2) serially-connected flip-flops, and an address control circuit which generates an address enable signal in response to a clock signal and a command signal. Each of the (N/2) flip-flops is clocked to the address enable signal and sequentially latches an external address.

Address buffer having (N/2) stages

Integrated circuit memory devices include test mode control circuits to more efficiently route test data to a fewer number of output pins during test mode operation. The memory device may include first and second memory arrays having first and second pluralities of data lines electrically coupled thereto, respectively. First and second pluralities of latch units are also provided. The first plurality of latch units are electrically coupled together in series as a first pipelined latch unit and electrically coupled in parallel to the first memory array by the first plurality of data lines. The second plurality of latch units are electrically coupled together in series as a second pipelined latch unit and electrically coupled in parallel to the second memory array by the second plurality of data lines. A preferred test mode control circuit electrically couples an output of the first pipelined latch unit to an input of the second pipelined latch unit, in response to a test mode control signal (.phi.DAE). This test mode control circuit enables the transfer of data from the first pipelined latch unit to the second pipelined latch unit during direct access test mode reading operations. This data can then be transferred from the first pipelined latch unit to an output driver and then serially transmitted to a single input/output pin. Additional memory arrays within the memory device may also be linked together during test mode operation to improve testing efficiency when multiple memory devices are tested simultaneously in a memory testing apparatus.

Integrated circuit memory devices having direct access mode test

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Seoul, South Korea

Joon-wan Chai