Sungkyunkwan University

Joon-sung Yang

Hyunseung Han

An error check and correction method of a 3D memory include a) storing check bits, which is used for error check and correction of an upper memory among the plurality of the memory layers, in one or more of spare cell arrays of a lower memory layer stacked below the upper memory layer and the upper memory layer; and b) performing error check and correction of the upper memory layer by using the stored check bits, wherein in the 3D memory, there are stacked a plurality of memory layers comprising a memory cell array with a matrix structure consisting of memory cells and a spare cell array with a matrix structure consisting of spare memory cells for replacing a fault memory cell, in which a fault occurs, and the 3D memory comprises a master layer for controlling the plurality of the memory layers.

3D memory with error checking and correction function

A method of improving an error checking and correction performance of a memory includes replacing a defective column including a defective memory cell of the memory cell array with a spare column of a the spare cell array, wherein the memory cell array includes memory cells in a matrix and the spare cell array includes spare memory cells in a matrix to be replaced for defective memory cells; storing check bits of error correction code in at least one memory cell of the defective column; storing defect information regarding a defect of the defective memory cell; determining whether the at least one memory cell storing the check bits is to be used to perform error checking and correction on a memory, based on the defect information; and performing error checking and correction on the memory using a memory cell selected based on a result of determining whether the at least one memory cell storing the check bits is to be used.

Method of improving error checking and correction performance of memory

A three-dimensional (3D) integrated circuit (IC) includes a plurality of through silicon vias (TSVs) configured to provide paths via which digital signals are transmitted or received; at least one redundant TSV configured to provide a path via which a digital signal to be transmitted or received via a failed TSV with a defect among the plurality of TSVs is transmitted or received; a digital-to-analog converter (DAC) configured to convert a digital signal transmitted via the at least one redundant TSV into an analog signal; an analog-to-digital converter (ADC) configured to convert an analog signal received via the at least one redundant TSV into a digital signal; and a multilevel modulator configured to perform multilevel modulation on a digital signal transmitted via the at least one redundant TSV.

Growing community of inventors

Seongnam-si, South Korea

Joon-sung Yang