Skhynix Inc.

Joon Seop Sim

Nam Kyun Park

Hyun Jeong Lee

Soo Gil Kim

Myoung Sub Kim

Sung Cheoul Kim

Gap Sok Do

Soo Hong Ahn

Eui Cheol Lim

Hyeong Soo Kim

Myung Hyun Rhee

A system for classifying data may include a memory, and a processor configured to determine a scan target including a data group selected from among data groups stored in the memory, based on a result of a comparison between first similarities of data groups stored in the memory and an externally received query, and a minimum value of second similarities of pieces of data included in a data group having a maximum value of the first similarities and the query, and to output, as result data responding to the query, scan data selected depending on a reference number of pieces of scan data from among pieces of scan data in the data group included in the scan target.

System for classifying data based on a classification algorithm and method of operating the same

A memory system for efficiently processing data in performing a job may include a plurality of memory devices configured to store data, a main data processor configured to access the plurality of memory devices, a sub data processor group including a plurality of sub data processors each configured to access the plurality of memory devices, respectively, a host interface configured to receive, from a host, a request for a job, and a job controller configured to perform the job by using one of the main data processor and the sub data processor group depending on whether accesses to the plurality of memory devices are related to each other for the job.

Memory system and method of operating the same

Methods, systems, and devices for alleviating a bandwidth bottleneck during an embedding operation are described. An example storage device, based on the disclosed technology, includes a memory device configured to store matrix data, a memory controller, coupled to the memory device, configured to receive, from a host, non-zero data and the index of the non-zero data, and generate vector data based on the non-zero data and the index, and an operating component, coupled to the memory device and the memory controller, configured to perform a multiplication operation between the matrix data and the vector data.

Storage device and method of operating the same

The present disclosure relates to a computing system. The computing system may include a memory system including a plurality of memory devices configured to store raw data and a near data processor (NDP) configured to receive the raw data by a first bandwidth from the plurality of memory devices and generate intermediate data by performing a first operation on the raw data, and a host device coupled to the memory system by a second bandwidth and determining a resource to perform a second operation on the intermediate data based on a bandwidth ratio and a data size ratio.

Computing system for determining resource to perform operation on data and operating method thereof

A computing system capable of reducing data movement during an embedding operation and efficiently processing the embedding operation includes a host and a memory system. The host divides a plurality of feature tables, each including a respective plurality of embedding vectors for a respective plurality of elements, into a first feature table group and a second feature table group; generates a first embedding table configured of the first feature table group; and sends a request for a generation operation of a second embedding table configured of the second feature table group to the memory system. The memory system generates the second embedding table according to the generation operation request provided by the host. The host divides the plurality of feature tables into the first feature table group and the second feature table group based on the number of elements included in each of the plurality of feature tables.

Host performing an embedding operation and computing system including the same

A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a semiconductor substrate having an active island, a gate buried in a predetermined portion of the active island, a source and a drain formed at both sides of the gate, and a current blocking layer formed in the active island corresponding to a lower portion of the drain. When current flows in from the drain, the current blocking layer is configured to discharge the current into the inside of the semiconductor substrate through a lower portion of the source.

Semiconductor integrated circuit apparatus and method of manufacturing the same

A semiconductor integrated circuit device, a method of manufacturing the same, and a method of driving the same are provided. The device includes a semiconductor substrate, an upper electrode extending from a surface of the semiconductor substrate; a plurality of switching structures extending from both sidewalls of the upper electrode in a direction parallel to the surface of the semiconductor substrate, and a phase-change material layer disposed between the plurality of switching structures and the upper electrode.

Growing community of inventors

Gyeonggi-do, South Korea

Joon Seop Sim