Samsung Electronics Co., Ltd.

Joon-Seok Moon

Hyun-Jung Lee

Dongsoo Woo

Sung-Sam Lee

Dong-Soo Woo

Jae-Rok Kahng

Makoto Yoshida

Jinwoo Lee

Chul Ho Lee

Sang-hyun Lee

Sung-Il Cho

Kyoung-Sub Shin

Hyun-Seung Song

Kirill Sokolov

Hyeoung-Won Seo

Kyo-Suk Chae

Cheol-Kyu Lee

Kyoung-Ho Jung

Hong Seok Cho

Jun-ho Yoon

Sung Won Yoo

Jaerok Kahng

Se-Keun Park

Keeshik Park

Kung-Hyon Nam

Seol-Min Yi

Dae-Hyun Moon

Dong Sik Kong

Hee Sun Joo

Young-Ju Choi

Young-Chol Lee

A semiconductor device, and a method of fabricating the semiconductor device including forming on a substrate a device isolation layer defining a plurality of active regions; and forming a plurality of gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming on the substrate a trench that intersects the active regions; forming a work-function control layer on a sidewall and a bottom surface of the trench; forming a conductive layer on the work-function control layer; sequentially forming a barrier layer and a source layer on the work-function control layer and the conductive layer, the source layer including a work-function control element; and diffusing the work-function control element from the source layer into an upper portion of the work-function control layer.

Semiconductor device and method of fabricating the same

A semicondcutor device, and a method of fabricating the semiconductor device including forming on a substrate a device isolation layer defining a plurality of active regions; and forming a plurality of gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming on the substrate a trench that intersects the active regions; forming a work-function control layer on a sidewall and a bottom surface of the trench; forming a conductive layer on the work-function control layer; sequentially forming a barrier layer and a source layer on the work-function control layer and the conductive layer, the source layer including a work-function control element; and diffusing the work-function control element from the source layer into an upper portion of the work-function control layer.

A semiconductor device includes a substrate, device isolation film defining an active region of the substrate in which a gate trench extends, a gate insulating film disposed along sides and a bottom of the gate trench, a gate electrode disposed on the gate insulating film in the gate trench and having a first portion, a second portion on the first portion, and a third portion on the second portion, a first barrier film pattern interposed between the first portion of the gate electrode and the gate insulating film, a second barrier film pattern interposed between the second portion of the gate electrode and the gate insulating film, and a third barrier film pattern interposed between the third portion of the gate electrode and the gate insulating film. The work function of the first barrier film pattern is greater than the work function of the second barrier film pattern and less than the work function of the third barrier film pattern.

Semiconductor device

The semiconductor device includes a substrate, a trench formed in the substrate, a gate insulation layer conformally formed on the inner surface of the trench, buried gate electrodes formed on the gate insulation layer and filling a portion of the trench, and a capping layer formed on the buried gate electrodes and filling the trench. The buried gate electrode include a first gate electrode and a second gate electrode surrounding a bottom portion of the first gate electrode, and an air gap is provided between a top portion of the first gate electrode and the gate insulation layer.

Semiconductor device and fabricating method thereof

Methods of fabricating semiconductor device are provided including forming first through third silicon crystalline layers on first through third surfaces of an active region; removing the first silicon crystalline layer to expose the first surface; forming a bit line stack on the exposed first surface; forming bit line sidewall spacers on both side surfaces of the bit line stack to be vertically aligned with portions of the second and third silicon crystalline layers of the active region; removing the second and third silicon crystalline layers disposed under the bit line sidewall spacers to expose the second and third surfaces of the active region; and forming storage contact plugs in contact with the second and third surfaces of the active region.

Methods of fabricating semiconductor devices having increased areas of storage contacts

Semiconductor devices and dynamic random access memory devices including a buried gate electrode are provided, the semiconductor devices include a substrate with a gate trench, a buried gate electrode partially filling the inside of the gate trench, a capping layer pattern in the gate trench and over the buried gate electrode, source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode, and a gate insulation layer interposed between the trench and the buried gate electrode. The capping layer pattern includes a high-k material layer that directly contacts an upper surface of the buried gate electrode.

Semiconductor devices and dynamic random access memory devices including buried gate pattern with high-k capping layer

Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer.

Method of forming recess and method of manufacturing semiconductor device having the same

In a semiconductor device and a method of manufacturing the same, a substrate is defined into active and non-active regions by a device isolation layer and a recessed portion is formed on the active region. A gate electrode includes a gate insulation layer on an inner sidewall and a bottom of the recessed portion, a lower electrode on the gate insulation layer and an inner spacer on the lower electrode in the recessed portion, and an upper electrode that is positioned on the inner spacer and connected to the lower electrode. Source and drain impurity regions are formed at surface portions of the active region of the substrate adjacent to the upper electrode. Accordingly, the source and drain impurity regions are electrically insulated by the inner spacer in the recessed portion of the substrate like a bridge, to thereby sufficiently prevent gate-induced drain leakage (GIDL) at the gate electrode.

Semiconductor device and method of manufacturing the same

A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.

Method of fabricating semiconductor device for reducing thermal burden on impurity regions of peripheral circuit region

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Seoul, South Korea

Joon-Seok Moon