Samsung Electro-mechanics Co., Ltd.

Joon Seok Kang

Sung Yi

Young Do Kweon

Sang Kee Yoon

Sung Cheon Jung

Hyun Kee Lee

Hong Won Kim

Jung Hyun Lee

Tae Sung Jeong

Yoon Shik Hong

Young Ho Kim

Jin Gu Kim

Suk Kee Hong

Jingli Yuan

Young Gyu Lee

The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof and provides a chip embedded printed circuit board including: an insulating layer having vias formed therethrough; a first chip and a second chip embedded in the insulating layer and having pads, which are respectively exposed to upper and lower surfaces of the insulating layer, on one surfaces thereof; an upper pattern formed on the upper surface of the insulating layer to be connected to the pads of the first chip and the vias; and a lower pattern formed on the lower surface of the insulating layer to be connected to the pads of the second chip and the vias. Also, the present invention provides a manufacturing method of a chip embedded printed circuit board.

Method of manufacturing a chip embedded printed circuit board

The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof. The present invention provides the chip embedded printed circuit board including an insulating layer embedding a chip provided with posts at an upper part, vias formed through the insulating layer, upper patterns formed at the upper part of the insulating layer to be connected to the posts and the vias and lower patterns formed at a lower part of the insulating layer to be connected to the vias, and the manufacturing method thereof.

Disclosed herein is a die package including an encapsulated die, including: a die including pads on one side thereof; an encapsulation layer covering lateral sides of the die; a support layer covering the encapsulation layer and one side of the die; a passivation layer formed on the other side of the die such that the pads are exposed therethrough; and a redistribution layer formed on the passivation layer such that one part thereof is connected with the pad. Here, since one side of the die is supported by the support layer and the encapsulation layer is formed on only the lateral side of the die, the warpage of the die package due to the difference in thermal expansion coefficient can be minimized.

Die package including encapsulated die and method of manufacturing the same

Disclosed herein are a wafer level package for heat dissipation and a method of manufacturing the same. The wafer level package includes a heat dissipation plate including a cavity and a hole, a die including a pad disposed in the cavity of the heat dissipation plate in a face-up manner, a thermal conductive adhesive disposed between the die and an inner wall of the cavity and disposed in the hole, and a redistribution layer connected at one end to the pad and at the other end extended. The wafer level package protects the die from external environments and enables the die to be easily flush with the heat dissipation plate.

Wafer Level package for heat dissipation and method of manufacturing the same

A wafer level package includes a chip, a removable resin layer, a molding material, a dielectric layer, redistribution lines and a solder resist. The removable resin layer is formed to surround side surfaces and a lower surface of the chip. The molding material is formed on the lower surface of the removable resin layer. The dielectric layer is formed over the removable resin layer including the chip and having via holes to expose portions of the chip. The redistribution lines are formed on the dielectric layer including insides of the via holes to be connected to the chip. The solder resist layer is formed on the dielectric layer to expose portions of the redistribution lines.

Wafer level package with removable chip protecting layer

Disclosed herein are a die package and a method of manufacturing the die package. A solder layer is formed on a lower surface of a die. The die is self-aligned and attached to a support plate using surface tension between the solder layer and a metal layer of the support plate, thus reducing attachment lead time of the die.

Die package and method of manufacturing the same

An MEMS variable optical attenuator includes a substrate having a planar surface, a micro-electric actuator arranged on the planar surface of the substrate, a pair of coaxially aligned optical waveguides having a receiving end and a transmitting end, respectively, and an optical shutter movable to a predetermined position between the receiving end and the transmitting end of the optical waveguides, and driven by the micro-electric actuator. A surface layer is formed on the optical shutter, has reflectivity less than 80% so as to allow incident light beams to partially transmit thereinto, and further has a sufficient light extinction ratio, thereby extinguishing the partially transmitted light beams therein.

Microelectromechanical systems (MEMS) variable optical attenuator

A dicing method for a micro electro mechanical system chip, in which a high yield and productivity of chips can be accomplished, resulting from preventing damage to microstructures during a dicing process by using a protective mask. The dicing method for a micro electro mechanical system chip, comprising the steps of designing a grid line and wafer pattern on a chip-scale on the non-adhesive surface of a transparent tape as a protective mask (first step); sticking microstructure-protecting membranes on the adhesive surface of the transparent tape (second step); putting the transparent tape on the whole surface of a wafer in a state wherein the grid line designed on the non-adhesive surface of the transparent tape is matched to the dicing line of the wafer (third step); cutting the transparent tape to a size larger than the wafer, mounting the wafer on a guide ring and dicing the wafer (fourth step); and separating the transparent tape from diced chips (fifth step).

Dicing method for micro electro mechnical system chip

Disclosed herein is an optical switch. The optical switch includes an electrostatic actuator and a substrate. The electrostatic actuator includes an electrostatic actuator, the electrostatic actuator comprising, a reciprocating mass located in the center of the electrostatic actuator, first rotating axes located symmetrically at the left and right sides of the reciprocating mass, first rotating masses rotatably connected to the first rotating axes, first rotating springs for supporting the first rotating masses, linear springs connected to the first rotating masses, second rotating masses connected to the linear springs, second rotating springs for supporting the second rotating masses, second rotating axes connected to the second rotating masses, structural anchors at the side ends of the actuator, drive electrodes, and a micro mirror movable by the same displacement as the reciprocating mass.

Growing community of inventors

Gyunggi-do, South Korea

Joon Seok Kang