Samsung Electronics Co., Ltd.

Hongik University Industry-academia Cooperation Foundation

Mogam Biotechnology Research Institute

Joon-Sang Park

Chang-ki Hong

Yong-Ho Ha

Suk-Hun Choi

Bo-un Yoon

Hyeong-Geun An

Sung-lae Cho

Yoon-Ho Son

Young-Soo Lim

Young-Lim Park

Won-Jun Lee

Jeong-Hee Park

Dong-Ho Ahn

Doo-Hwan Park

Ho-young Kim

Jun-Young Jang

Han-Bong Ko

Sang-yong Kim

Dong-Won Lim

Hyun-Suk Kwon

Myung-jin Kang

Gyeo-Re Lee

Jong-Won Lee

Jun-Soo Bae

Seung-Ho Park

Sung-Un Kwon

Byoung-ho Kwon

Byoung-Moon Yoon

Chang-Ki Hong

Jae-Kwang Choi

Ki-Hyung Ko

Jun-Youl Yang

Chung-Ki Min

Dong-keun Kim

Hong-Mo Moon

Yung-Dae Yun

Myung-Jung Pyo

Yeol Jon

Tae-eun Kim

Se-Rah Yun

Jung-Seob Kim

Chang-sun Hwang

Sang-Chul Bai

Mi-Kyung Min

Provided are a data transmission system, an encoding apparatus, and a decoding method. The encoding apparatus includes an encoding unit configured to use an encoding matrix to encode original packets sequentially generated from a codec to generate an encoded packet in units of a generation. The encoding unit is configured to use information provided from the codec to dynamically determine a generation boundary of the original packets to encode the original packets. The encoding unit is configured to dynamically a generation size according to a generation time of the original packets. According to embodiments of the inventive concept, it is possible to use information provided from a VoIP codec to dynamically determine the boundary or size of a generation to decrease a standby time upon encoding/decoding, and may recover the loss of packets that may occur in a wired/wireless network.

Data transmission system, encoding apparatus and encoding method

A nonvolatile memory cell includes a substrate and a phase changeable pattern configured to retain a state of the memory cell, on the substrate. An electrically insulating layer is provided, which contains a first electrode therein in contact with the phase changeable pattern. The first electrode has at least one of an L-shape when viewed in cross section and an arcuate shape when viewed from a plan perspective. A lower portion of the first electrode may be ring-shaped when viewed from the plan perspective. The lower portion of the first electrode may also have a U-shaped cross-section. An upper portion of the first electrode may also have an arcuate shape that spans more than 180&#xb0; of a circular arc.

Nonvolatile memory cells having phase changeable patterns therein for data storage

In an etching method, a thin layer is formed on a first surface of a first substrate doped with first impurities having a first doping concentration. The thin layer is doped with second impurities having a second doping concentration lower than the first doping concentration. A second substrate is formed on the thin layer. A second surface of the first substrate is polished. The polished first substrate is cleaned using a cleaning solution including ammonia and deionized water. The cleaned first substrate is etched to expose the thin layer.

Etching methods and methods of manufacturing a CMOS image sensor using the same

A method of fabricating a phase change memory device includes the use of first, second and third polishing processes. The first polishing process forms a first contact portion using a first sacrificial layer and the second polishing process forms a phase change material pattern using a second sacrificial layer. After removing the first and second sacrificial layers to expose resultant protruding structures of the first contact portion and the phase change material pattern, a third polishing process is used to polish the resultant protruding structures using an insulation layer as a polishing stopper layer.

Method fabricating semiconductor device using multiple polishing processes

A chemical-mechanical polishing (CMP) method of polishing a phase-change material and a method of fabricating a phase-change memory, the CMP method including forming the phase-change material on an activation surface of a semiconductor wafer, and performing a CMP process on the phase-change material using a polishing pad, wherein the performing the CMP process includes reducing a change in the composition of the phase-change material by adjusting, within a predetermined range, a temperature of a region where the semiconductor wafer and the polishing pad contact each other.

Chemical-mechanical polishing method for polishing phase-change material and method of fabricating phase-change memory device using the same

A phase changeable memory unit includes a lower electrode, an insulating interlayer structure having an opening, a phase changeable material layer and an upper electrode. The lower electrode is formed on a substrate. The insulating interlayer structure has an opening and is formed on the lower electrode and the substrate. The opening exposes the lower electrode and has a width gradually decreasing downward. The phase changeable material layer fills the opening and partially covers an upper face of the insulating interlayer structure. The upper electrode is formed on the phase changeable material layer.

Method of manufacturing a phase changeable memory unit having an enhanced structure to reduce a reset current

A contact structure that includes a first pattern formed on a substrate, wherein the first pattern has a recessed region in an upper surface thereof, a planarized buffer pattern formed on the first pattern, and a conductive pattern formed on the planarized buffer pattern.

Contact structure, a semiconductor device employing the same, and methods of manufacturing the same

Phase change memory devices can have bottom patterns on a substrate. Line-shaped or L-shaped bottom electrodes can be formed in contact with respective bottom patterns on a substrate and to have top surfaces defined by dimensions in x and y axes directions on the substrate. The dimension along the x-axis of the top surface of the bottom electrodes has less width than a resolution limit of a photolithography process used to fabricate the phase change memory device. Phase change patterns can be formed in contact with the top surface of the bottom electrodes to have a greater width than each of the dimensions in the x and y axes directions of the top surface of the bottom electrodes and top electrodes can be formed on the phase change patterns, wherein the line shape or the L shape represents a sectional line shape or a sectional L shape of the bottom electrodes in the x-axis direction.

Methods of forming phase change memory devices having bottom electrodes

Methods of fabricating phase change memory elements include forming an insulating layer on a semiconductor substrate, forming a through hole penetrating the insulating layer, forming a lower electrode in the through hole and forming a recess having a sidewall comprising a portion of the insulating layer by selectively etching a surface of the lower electrode relative to the insulating layer. A phase change memory layer is formed on the lower electrode. The phase change memory layer has a portion confined by the recess and surrounded by the insulating layer. An upper electrode is formed on the phase change memory layer. Phase change memory elements are also provided.

Phase change memory elements having a confined portion of phase change material on a recessed contact

A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks. The method further includes etching the portion of the insulation layer exposed by the opening region using the first and second etching masks to form a plurality of opening holes, removing the second etching mask, forming a conductive layer filling the opening holes to cover the remaining first etching masks and performing a chemical mechanical polishing (CMP) process on the conductive layer using the capping layer as a polishing end point to remove the first etching masks such that a plurality of SAC pads separated from each other are formed that fill the opening holes.

Method of fabricating self-aligned contact pad using chemical mechanical polishing process

A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug. Phase-change memory devices formed by such techniques are also discussed.

Microelectronic devices using sacrificial layers and structures fabricated by same

Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the tops of the first mask patterns and the second mask patterns have planar surfaces. After the planarization of the sacrificial layer, the remaining the sacrificial layer may be removed by an ashing process.

Method of forming self-aligned double pattern

Methods of fabricating phase change memory elements having a confined portion of phase change material on a recessed contact

Method for forming small features in microelectronic devices using sacrificial layers

Growing community of inventors

Seoul, South Korea

Joon-Sang Park