Samsung Electronics Co., Ltd.

Lg Display Co., Ltd.

Joon-Min Park

Woo-Yeong Cho

Hyung-Rok Oh

Sang-beom Kang

Kwang-Jin Lee

Chang-Soo Lee

Qi Wang

Hui-kwon Seo

Du-Eung Kim

Hui-Kwon Seo

Byung-Gil Choi

Beak-Hyung Cho

Choong-Keun Kwak

Won-Seok Lee

Jihun Kim

Jongsik Shim

ChangHo Oh

Gong-Heum Han

Sang-Beom Kang

Hyung-rok Oh

Young-Kug Moon

SungJin Hong

Sikyu Lee

Haeyoon Kang

A display apparatus includes a display panel including data lines extending in a first direction, gate lines extending in a second direction which differs from the first direction, and unit pixels connected to the data lines and the gate lines, wherein each of the unit pixels includes a white pixel and a plurality of color pixels, an nwhite pixel arranged at an nposition among white pixels arranged in the first direction is connected to an odd white data line (where n is an odd number), and an n+1white pixel arranged at an n+1position among white pixels arranged in the first direction is connected to an even white data line.

Display apparatus

A display device includes: a display panel having a plurality of sub-pixels sharing a single reference voltage line, each of the sub-pixels comprising a switching transistor, a driving transistor, a sensing transistor, a storage capacitor, and a light-emitting element; a data driver configured to supply a data voltage to the plurality of sub-pixels; a gate driver configured to supply a gate signal to the plurality of sub-pixels; a timing controller configured to control the data driver and the gate driver; and a detector configured to sense a threshold voltage and mobility of the driving transistor to detect if there is a short-circuit between a gate electrode and an output terminal of the driving transistor.

Display device and method for driving the same

A display device includes a display panel having a plurality of gate lines, a plurality of data lines, and a plurality of subpixels; a gate driver circuit driving the plurality of gate lines; a data driver circuit driving the plurality of data lines; and a timing controller controlling signals applied to the gate driver circuit and the data driver circuit, wherein the timing controller controls the data driver circuit for a black data to be applied to at least one of designated subpixels among the plurality of subpixels, and controls the gate driver circuit for a gate signal, which is a signal for sensing a characteristic of a driving transistor of the designated subpixel, to be applied in an interval between times at which the black data are applied, such that the gate signal does not overlap the black data.

Display device and method of driving the same

A display device and a method of driving the same. Characteristics of driving transistors disposed in subpixels of a display panel are sensed and compensated for, thereby improving the image quality of the organic light-emitting display device. Changes in a data voltage between a point in time at which a blank period starts and a period in which the sensing of the driving transistors starts are reduced or minimized, thereby reducing deviations in the sensing of the characteristics of the driving transistors.

In a display device, an edge portion of a pixel electrode is modified. A valley is provided in an overcoat layer located below the pixel electrode. The edge portion of the pixel electrode is configured to be curved or bent onto the overcoat layer. As a result, the aperture ratio of the display device can be increased, and an image abnormality in the edge portion of the pixel electrode can be prevented.

Display device

A display device can include a display panel, in which a subpixel including a transistor where data lines and gate lines intersect, is disposed; a gate driving unit that sequentially outputs a gate signal to the gate lines; a data driving unit that outputs a data voltage to the data lines according to the gate signal provided to each gate line, and outputs to the data lines during a blank time before a specific frame, data voltages having an output waveform that is identical to data voltages of at least one gate line of the specific frame; and a timing controller that controls the gate driving unit and the data driving unit, and performs a pixel compensation which changes data provided to each subpixel.

Disclosed are a transistor structure for a display and an organic light emitting display device. The transistor structure includes: a voltage line positioned in one direction and configured to supply voltage to pixels; and two or more transistors which share one of drains and sources which are formed integrally with the voltage line and respectively include the other of the drains and sources which are individually formed and connected with different nodes directly or through a connection pattern.

Display device and transistor structure for the same

The present invention provides an organic light emitting display device that includes a display panel in which an organic light emitting diode and a driving circuit are disposed in each pixel area of a first pixel and a second pixel which are certain pixels among a plurality of pixels, a floating pattern insulated from at least one of a first electrode of the organic light emitting diode of the first pixel and a first electrode of the organic light emitting diode of the second pixel is formed in the display panel, or a connection pattern for electrically connecting the first electrode of the organic light emitting diode of the first pixel with the first electrode of the organic light emitting diode of the second pixel is formed.

Organic light emitting display device having repair structure

A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

Memory device and system with improved erase operation

Method of erasing a memory including first and second erase modes

Memory device using a variable resistive element

Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using an internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

Nonvolatile memory, memory system, and method of driving

The phase change memory device includes a plurality of memory banks, a plurality of local conductor lines connected to the plurality of memory banks, at least one global conductor line connected to the plurality of local conductor lines, and at least one repair control circuit configured to selectively replace at least one of the at least one global conductor line with at least one redundant global conductor line and configured to selectively replace at least one of the plurality of local conductor lines with at least one redundant local conductor line.

Phase change memory

Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using a first internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

The present invention provides a nonvolatile memory device that uses a resistance material. The nonvolatile memory device includes: a stacked memory cell array having a plurality of memory cell layers stacked in a vertical direction, the stacked memory cell array having at least one memory cell group and at least one redundancy memory cell group; and a repair control circuit coupled to the stacked memory cell array, the repair control circuit configured to repair a defective one of the at least one memory cell group with a selected one of the at least one redundancy memory cell group. The features that enable repair improve the fabrication yield of the nonvolatile memory device.

Growing community of inventors

Seoul, South Korea

Joon-Min Park