Advanced Micro Devices Corporation

Joon Kit Goh

Boon Piaw Tan

L S Chua

Jacques Ah Wong

Beng Chew Khou

A method and apparatus for automatically verifying whether a network interface is transmitting frame data properly. Frame data stored in host memory is transmitted to the network interface and to a transmit data checker. The network interface receives, processes and transmits the frame data. The processed frame data is transmitted to a network media and to the transmit data checker. The transmit data checker compares the frame data from the host memory with the processed frame data from the network interface and generates an indicator signal. The indicator signal indicates whether the network interface is transmitting processed frame data properly. The indicator signal is sent to a display which displays the result. The transmit data checker includes a timer for determining the processing time of the network interface. The timer measures the time between reception of the frame data from the host memory and the reception of the transmitted data.

Method and apparatus for automatic transmit verification

A method and apparatus for automatically verifying whether a network interface is receiving frame data properly. A network interface and a received data checker receive frame data from a network media such as a network or a network model. The network interface processes and transmits the frame data to host memory for storage. The host memory stores the frame data and transmits the frame data to the receive data checker. The receive frame checker compares the frame data from the host memory with the frame data from the network media and generates an indicator signal. The indicator signal indicates whether the network interface is receiving frame data properly. The indicator signal is sent to a display which displays the result.

Method and apparatus for automatic receive verification

A method for testing and verifying an integrated circuit using a bottom-up approach to generate a complete integrated circuit. The design for an integrated circuit is divided or defined into individual sub-system modules which are then tested either individually or as a combination of sub-system modules (e.g., a partially integrated circuit). Once all of the sub-system modules are tested and verified, the sub-system modules can be combined to form a complete integrated circuit which can then be tested. Each of the sub-system modules, the partially integrated circuit and the complete integrated circuit are tested and verified.

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Singapore, Singapore

Joon Kit Goh