Qualcomm Incorporated

Joon Hyung Chung

Mikhail Popovich

Yuancheng Christopher Pan

Gudoor Reddy

Xiongfei Meng

Yuancheng Chris Pan

Juan Sebastian Ochoa Munoz

The place and route stage for a hard macro is modified to assign a more robust power-grid tier to a critical path for a hard macro and to assign a less robust power-grid tier to a remainder of the hard macro.

Adaptive multi-tier power distribution grids for integrated circuits

The place and route stage for a hard macro including a plurality of tiles is modified so that some of the tiles are assigned a more robust power-grid tier and so that others ones of the tiles are assigned a less robust power-grid tier.

A power delivery network (PDN) including a battery, a set of regulators for generating supply voltages, and an integrated circuit (IC) including power rails configured to receive the supply voltages. The IC further includes an IC chip having a set of cores. The power rails includes a larger rail configured to provide a full range of currents, and the other smaller power rails each configured to provide lower range of currents. The IC includes multiplexers having first inputs coupled respectively to the smaller rails, second inputs coupled to the larger rail, and outputs coupled to the cores. When the smaller rail is able to supply the current needed by a core, the multiplexer is configured to couple the smaller rail to the core. When the smaller rail cannot supply the current needed by the core, the multiplexer is configured to couple the larger rail to the core.

System and method for reducing power delivery network complexity through local power multiplexers

An apparatus including a conductive stack structure includes an Mlayer interconnect on an Mlayer and extending in a first direction on a first track, an Mlayer interconnect on an Mlayer in which the Mlayer is a lower layer than the Mlayer, a first via stack coupled between the Mlayer interconnect and the Mlayer interconnect, a second via stack coupled between the Mlayer interconnect and the Mlayer interconnect, a second Mlayer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mlayer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mlayer interconnect is between the second Mlayer interconnect and the third Mlayer interconnect. The second Mlayer interconnect and the third Mlayer interconnect are uncoupled to each other.

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San Marcos, CA, United States of America

Joon Hyung Chung