Zaram Technology Co., Ltd.

Chung Ang University Industry Academic Cooperation

Lightworks Technology Inc

Joon Hyun Baek

Sung Hoon Park

In Shik Seo

Jae-Hun Jung

Kwang-Hyun Baek

Tae Jong Lee

Hong Chang Yeoh

Yun-Hwan Jung

Byoung Hoon Bae

The present invention relates to a hardware high-speed computation combined RISC-V based computation device for supporting a user-defined instruction set and a method thereof which configures a hardware high-speed computation unit executing a user-defined function through a field programmable gate array (FPGA) in a single chip together with a RISC-V based computation device, executes general computation and user-defined computation in an instruction level, not a separate bus connection configuration, through a program using a RISC-V based instruction set including a user-defined instruction set, and provides flexibility capable of optionally changing the user-defined instruction set and a corresponding function and a method thereof.

RISC-V implemented processor with hardware acceleration supporting user defined instruction set and method thereof

Provided are an apparatus and a method for resetting a transimpedance amplifier for low-power passive optical network equipment for improving the synchronization performance of an uplink burst signal by resetting the transimpedance amplifier for amplifying a received signal of an optical transceiver at a time point at which a frame of the uplink burst signal ends. There is an effect of improving the burst-mode clock and data reconstruction performance through simple analysis of a bit pattern and thus reducing a guard time or a number of repetitions of preambles by accurately identifying the time point at which the frame of the uplink burst signal ends without using a frame data analysis scheme to reset the transimpedance amplifier.

Apparatus and method for resetting transimpedance amplifier for low-power passive optical network equipment

Provided are a relay apparatus and a relay method for a passive optical network so as to largely extend a communicable distance while maintaining compatibility with existing network components. In the case of applying an optical relay to the passive optical network, a delay time is reduced by applying the optical relay so that entire transmission delay time considering the increased delay time may be within a preamble period of the upstream burst stream, thereby rapidly increasing a transmission distance of the passive optical network by using the optical relay.

Relay apparatus and relay method for passive optical network

The present invention relates to an input interface providing USB apparatus which is capable of providing an input interface for a variety of external devices in Bluetooth communication with the USB apparatus without a separate input means by connecting the USB apparatus to USB ports of a terminal and sharing an input means of the terminal with the external devices, and an interface providing method. The input interface providing USB apparatus and method in accordance with the present invention is capable of providing an input interface for a variety of external devices in Bluetooth communication with the USB apparatus without a separate input means by connecting the USB apparatus to USB ports of a terminal and sharing an input means of the terminal with the external devices, thereby providing excellent user convenience.

Input interface providing USB apparatus and interface providing method

The present invention relates to a digital to analog converter, to a return-to-zero digital to analog converter with improved wideband characteristics by enabling a return-to-zero output without separate clock and controller, and a converting method thereof. Since the return-to-zero digital to analog converter and the converting method thereof are capable of outputting an RZ output without directly providing a clock signal to an analog circuit by configuring a switch for generating a zero point signal and a differential pipeline for providing a differential signal to control the switch according to input digital data using a differential structure, the converter can provide wideband characteristics and high dynamic performance.

Return to zero digital to analog converter and converting method thereof

The present invention relates to a direct digital frequency synthesizer using a variable sine wave-weighted digital to analog converter with improved size and efficiency and a synthesizing method thereof. The direct digital frequency synthesizer and the synthesizing method thereof are capable of simplifying a configuration for matching output data of a phase accumulator to sine wave amplitude without increase in complexity of a DAC by applying a nonlinear DAC for directly generating a current corresponding to base points with sine weights and a variable sine wave-weighted DAC for generating fine currents to be combined with variable weights based on the base points. Accordingly, it is possible to provide a high quality output, reduce a size and power consumption, and increase a speed.

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Seongnam-si, South Korea

Joon Hyun Baek