Samsung Electronics Co., Ltd.

Other

Korea University Research and Business Foundation

Creven Co., Ltd.

Joon Hyuk Kim

Eun-Kuk Chung

Han-jin Lim

Jin-Hong Kim

Bong-hyun Kim

Suk-chul Bang

Yun-seung Kang

Dong-Kak Lee

Hyun Uk Park

Minhee Cho

Dongkyun Park

Junghwan Oh

Han-young Kim

Woo-soon Jang

Hag Dong Kim

Sang-Hoon Lee

Se Hyun Lee

Seong-soo Lee

Kang-ill Seo

Joon-Soo Park

Sang Yeol Kang

Hyongsoo Kim

Kyung-Tae Jang

Mansug Kang

Kukhan Yoon

Cheolhong Kim

Ki Yeon Park

Jong-Sun Ahn

Youn Soo Kim

Yung-Jun Kim

WonSeok Yoo

Seonghwee Cheong

Seokwoo Nam

Gyuwan Choi

Jae Hyoung Choi

Suk-Chul Bang

KiHong Nam

YongJoong Kim

Kyo Seop Kim

Cha Young Yoo

Chang Woo Sun

Jong-Seon Ahn

Hyung-Mo Yang

Gyu Hwan Oh

Chang-Yeon Yoo

Joon Youn Hwang

Ho Jun Kwon

Il Wong Kim

Hee-Woong Yang

The present invention relates to a cancer diagnostic apparatus for checking a cancer incidence by allowing an antibody (captured antibody), which reacts with an rpS3 (ribosomal protein S3; antigen) capable of checking a phenomenon of a cancer, to react with the rpS3, and performing concentration measurement after extracting an emission signal of the reacted antigen (rpS3), and a cancer diagnostic system using the cancer diagnostic apparatus. The cancer diagnostic system includes: the cancer diagnostic apparatus for irradiating an ultraviolet ray (UV) from a bottom of a bio-chip provided with an antibody reacting with an antigen (ribosomal protein S3; rpS3), making an image from a visible ray obtained from the ultraviolet ray, which is converted by the antigen and the antibody bound to each other while passing through the bio-chip, and extracting only a specific frequency color from the visible ray to generate cancer diagnosis information; and a user terminal.

Cancer diagnostic apparatus and cancer diagnostic system using the same

An apparatus adjusting saddle angle for bicycle includes an elastic member forward a central axis in a longitudinal direction of a seat post, a lower body coupled to the seat post and protruding forward to support the elastic member, and an upper body including a saddle coupling portion to the saddle, supporting upper end of the elastic member on upper portion, and hinge-coupled to the lower body to rotate in rotation axis such that the saddle angle is changed for the lower body fixed to the seat post by external force. The elastic member and the rotation axis are in front and rear of the centerline of the lower body, respectively. The saddle coupling portion is in front of the centerline of the lower body and rear of the elastic member, and above the rotation axis. Thus, saddle angle is easily adjusted to improve user's convenience and riding comfort.

Apparatus of adjusting saddle angle for bicycle

A semiconductor device is provided including a base insulating layer on a substrate; a first conductive line that extends in a first direction on the base insulating layer; data storage structures on the first conductive line; selector structures on the data storage structures, each of the selector structures including a lower selector electrode, a selector, and an upper selector electrode; an insulating layer in a space between the selector structures; and a second conductive line disposed on the selector structures and the insulating layer and extended in a second direction intersecting the first direction. An upper surface of the insulating layer is higher than an upper surface of the upper selector electrode.

Semiconductor devices including data storage patterns

An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.

Electrode structure, method of fabricating the same, and semiconductor device including the electrode structure

The present invention relates to a pharmaceutical composition for inhibiting cancer cell metastasis, the pharmaceutical composition including at least one of: (1) si-rpS3/203 binding to a 203base sequence of rpS3 mRNA; (2) si-rpS3/635 binding to a base sequence corresponding to a position 635 of the rpS3 mRNA; (3) si-rpS3/747 binding to a base sequence corresponding to a position 747 of the rpS3 mRNA; and (4) si-rpS3/766 binding to a base sequence corresponding to a position 766 of the rpS3 mRNA.

Pharmaceutical composition for inhibition of cancer cell metastasis including siRNA for ribosomal protein S3

The present invention relates to a small interference RNA (siRNA) for specifically inhibiting the expression of ribosomal protein in cells, and more particularly, to an siRNA that specifically inhibits the expression of endogenous rpS3 protein in cells without influencing tagged overexpressed protein. The siRNAs of the present invention are excellent in terms of economy and efficiency compared to conventional commercially available products.

Small interference RNA for inhibiting intracellular expression of ribosomal protein S3

A semiconductor device includes a plurality of capacitors disposed on a substrate and a support pattern supporting upper portions and lower portions of the capacitors. Each of the capacitors includes a lower electrode, an upper electrode, and a dielectric layer between the lower and upper electrodes. The lower electrode includes a first electrode portion electrically connected to the substrate and having a solid shape and a second electrode portion stacked on the first electrode portion and having a shape comprising an opening therein. The support pattern includes an upper pattern contacting sidewalls of top end portions of the lower electrodes and a lower pattern vertically spaced apart from the upper pattern. The lower pattern contacts sidewalls under the top end portions of the lower electrodes.

Semiconductor devices having hybrid capacitors and methods for fabricating the same

A method of fabricating a semiconductor device includes forming an etch-target layer on a substrate having an alignment key, forming a transparent first pattern on the etch-target layer to face the alignment key, forming an opaque second pattern on the etch-target layer to be adjacent to the first pattern, and etching the etch-target layer using the first pattern and the second pattern as an etch mask.

Methods of fabricating a semiconductor device

A semiconductor device with vertical channel transistors and a method of fabricating the same are provided. A method of fabricating the semiconductor device includes patterning a substrate to form a trench that defines an active region, forming a sacrificial pattern in a lower region of the trench, forming a spacer on an upper sidewall of the trench, recessing a top surface of the sacrificial pattern to form a window exposing a sidewall of the active region between the spacer and the sacrificial pattern, doping a sidewall of the trench through the window to form a doped region in the active region, and forming a wiring in the trench to be connected to the doped region.

Semiconductor device with vertical channel transistor and method of fabricating the same

A method of manufacturing a semiconductor device, the method including: preparing a semiconductor substrate including a mold layer and a support layer disposed on the mold layer; forming multiple holes that pass through the mold layer and the support layer; forming multiple bottom electrodes in the holes; exposing at least a portion of the bottom electrodes by removing at least a portion of the mold layer; removing a portion of the bottom electrodes from an exposed surface of the bottom electrodes; and sequentially forming a dielectric layer and a top electrode layer on the bottom electrodes.

Methods of manufacturing semiconductor devices

Methods of forming fine patterns are provided. The methods may include forming first hard mask patterns extending in a first direction on a lower layer, forming second hard mask patterns filling gap regions between the first hard mask patterns, forming first mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the first mask patterns as etch masks to form first openings, forming second mask patterns filling the first openings and extending in the second direction, and etching the second hard mask patterns using the second mask patterns as etch masks to form second openings spaced apart from the first openings in a diagonal direction with respect to the first direction.

Methods for forming fine patterns of a semiconductor device

A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.

Stacked semiconductor device and related method

Growing community of inventors

Seoul, South Korea

Joon Hyuk Kim