Samsung Electronics Co., Ltd.

Sejong University

Kwangwoon University Industry-Academic Collaboration Foundation

Joon Ho Song

Shi Hwa Lee

Min Soo Kim

Won Chang Lee

Doo Hyun Kim

Sang Jo Lee

Do Hun Kim

Dong Hoon Lee

Gi Ho Park

Hyun Ho Cho

Do-Hyung Kim

Dong Gyu Sim

Do Hyung Kim

Yong Seok Choi

Donggyu Sim

Jin Sub Lee

Sung Wook Jung

Sang June Lee

Jin Soo Cho

Eun Kyung Ryu

Jung Han Seo

Jeong Han Seo

Sung Uk Jeong

It is an aspect of the present disclosure to provide an image processing apparatus, a display apparatus and a method of controlling of the display apparatus capable of preventing a rapid decrease in the image quality of image data. In accordance with an example aspect of the present disclosure, a display apparatus comprises: a plurality of image processing modules, each image processing module configured to perform an image processing process; a controller configured to output image data processed by any one image processing module of the plurality of image processing modules, based on state information of the plurality of image processing modules; and a display configured to display the output image data.

Image processing apparatus, display apparatus and method of controlling thereof

A method and apparatus for applying a tile size adaptively based on a size of a coding unit. An image processing apparatus may detect a size of a largest coding unit (LCU) used in encoding of a video from a header of a bitstream, may determine a tile size adaptively based on the detected size of the LCU, and may decode the bitstream in units of the LCU based on the determined tile size.

Image processing apparatus and method

A reconfigurable processor and an operation method of the reconfigurable processor may include: a status register configured to store a status value used to determine at least one execution mode in a processor; a parallel processing scheduler configured to schedule at least one of a very long instruction word (VLIW) logic and a coarse grained architecture (CGA) logic to be used based on the stored status value; a VLIW register configured to store processed data according to the VLIW logic; and a CGA register configured to store processed data according to the CGA logic.

Reconfigurable processor for parallel processing and operation method of the reconfigurable processor

An arithmetic processing apparatus and method for high speed processing of an application are provided. The arithmetic processing apparatus may include a program control unit to store operation processing information necessary for application operation in a communication channel by executing an application code, and an operation processing unit to process the application operation using the operation processing information stored in the communication channel.

Arithmetic processing apparatus and method for high speed processing of application

An encoding/decoding apparatus and method for parallel correction of in-loop pixels based on complexity using a video parameter may include a complexity measuring unit to measure a complexity of an in-loop pixel correction process, using video codec parameter information, in a video codec, and a core allocating unit to evenly distribute jobs associated with the in-loop pixel correction process, using the measured complexity.

Encoding/decoding apparatus and method for parallel correction of in-loop pixels based on measured complexity, using video parameter

An apparatus and a method for dividing image data into partition slices and encoding and decoding the image data based on a correlation between macroblocks are provided. The macroblocks may be decoded in parallel and thus, it is possible to improve an overall image quality and processing speed.

Apparatus for dividing image data and encoding and decoding image data in parallel, and operating method of the same

An apparatus and method sequentially parses bitstreams based on a removal of an Emulation Prevention Byte (EPB). The apparatus and method may detect an EPB pattern from among sequentially input bitstreams, may store the bitstreams, may store a processed bitstream where the EPB pattern is removed, among the bitstreams, and may select an output of a register buffer based on an input of a buffer selection flag.

Apparatus and method for sequentially parsing bitstreams based on removal of emulation prevention byte

Disclosed are an apparatus and method of lossless compression and restoration of selective image information. The apparatus of lossless compression of selective image information may compress an uncompressed block image of image information without loss to convert the uncompressed block image into a compressed block image, and store the converted compressed block image.

Apparatus and method of lossless compression/restoration of selective image information

A method and apparatus for restoring an image by copying a memory may include determining whether to perform an interpolation operation based on block information, and restoring a current image using a reference image depending on whether to perform the interpolation operation.

Method and apparatus for restoring image by copying memory

A memory access address translating apparatus and method may each classify pixels included in an input image into a plurality of tiles, and may generate a new memory for each of the successive tiles to enable the successive tiles, among a plurality of tiles, to be stored in different banks.

Method and apparatus for translating memory access address

Provided is an apparatus and method of dynamically distributing load occurring in multiple cores that may determine a corresponding core to perform functions constituting an application program, thereby enhancing the entire processing rate.

Apparatus and method of dynamically distributing load in multiple cores

An image data decoding apparatus and method are based on an availability of reference data. The image data decoding apparatus may include a core to process decoding of image data, and an availability determining device to receive, from the core, availability verification request information with respect to a reference area of a first frame included in the image data, to determine an availability with respect to the reference area based on the received availability verification request information, and to transmit, to the core, the determined availability. When the reference area is available, the core may process decoding of a second frame based on the reference area.

Apparatus for decoding image data based on availability of reference data and method thereof

An apparatus and method provide parallel encoding and decoding of image data based on correlation of macroblocks. To encode and decode image data having a high resolution, an encoding order may be determined based on a correlation between blocks of the image data, and a decoding order may be determined based on the determined encoding order, thereby efficiently processing the blocks in parallel.

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Hwaseong-si, South Korea

Joon Ho Song