Samsung Electronics Co., Ltd.

Isoclear, Inc.

Joon-hee Lee

Hee-joo Choi

Youn-Cheul Kim

Byoung-sul Kim

Kae-Won Ha

In-sang Song

Dong-Jun Kim

Seung-Hee Lee

In-Ku Kang

Hyun-suk Kim

Kee-jeong Rho

Jun-Ho Jo

Byoung-hun Lee

Kwan-Yong Jin

Jae-in Song

Kyung-man Kim

Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes.

Non-volatile memory devices with vertically integrated capacitor electrodes

The semiconductor package includes: a package substrate comprising a bonding pad; a plurality of semiconductor chips stacked on the package substrate; and a bonding wire configured to electrically connect the semiconductor chips and the bonding pad. For at least one of the plurality of semiconductor chips: the semiconductor chip comprises: a semiconductor device; a first pad electrically connected to the semiconductor device; a conductive pattern; and a second pad electrically connected to the first pad, spaced apart from the conductive pattern, and extending over the conductive pattern; and the bonding wire is connected to the second pad.

Semiconductor package and method of forming

A semiconductor memory device having a mount test circuit and a mount test method thereof are provided. The test circuit for use in a semiconductor memory device including a plurality of memory blocks may include a comparison unit for comparing test data of at least two memory blocks selected from the plurality of memory blocks, deciding whether or not the test data of the selected memory blocks are identical, and outputting a pass signal or fail signal as a flag signal; and an output selection unit for selecting any one of the selected memory blocks as an output memory block, and changing the output memory block whenever the fail signal is generated from the comparison unit, thus forming it as a data output path, which may lessen error occurrence.

Semiconductor memory device having mount test circuits and mount test method thereof

A method and apparatus are provided for transmitting data more efficiently between stations in a power line communication (PLC) network while preventing a hidden node problem. The method of transmitting data includes: detecting a hidden node in a network; and transmitting at least one of a request to send (RTS) command and a clear to send command (CTS) to the network before transmitting the data, if a hidden node is detected and a transmitting station a data packet having a size which is larger than a predetermined size. Using the method, interference of data transmissions and a low data throughput caused by the hidden node problem should be prevented.

Method and apparatus for transmitting data in power line communication network while preventing hidden node problem

A semiconductor memory device and an operation control method thereof are provided. The method may comprise executing a control such that a precharge operating mode and an active operating mode may be successively performed in response to one pre-active command, thereby reducing the current consumption and loading of the system, and thus, enhancing system performance.

Semiconductor memory device and operation control method thereof

Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of data bits from a plurality of memory blocks. In addition, each comparison unit outputs data bits from one of the memory blocks within the respective memory chip.

Memory module with parallel testing

A memory system for controlling interface timing in a memory module and a related timing control method are disclosed. The memory system comprises a memory module having a memory module controller configured to control interface timing of a plurality of memory devices in accordance with memory information and memory signal information. The memory information includes memory initialization information and interface timing information for the plurality of memory devices.

System controlling interface timing in memory module and related method

Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X test data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of test data bits from a plurality of memory blocks. In addition, each comparison unit outputs test data bits from one of the memory blocks within the respective memory chip.

A chemical mechanical polishing (CMP) apparatus for planarizing a semiconductor wafer includes a wafer carrier for loading and fixing a semiconductor wafer to be polished and a polishing platen rotating at a constant speed, disposed at a lower portion of the wafer carrier. A polishing pad is provided on an upper surface of the polishing platen, and is in contact with a surface of the semiconductor wafer. A spiral slurry feed line supplies a slurry solution to the polishing pad. An end of the spiral slurry feed line is provided with a plurality of nozzles and the spiral slurry feed line is connected to a deionized water feed line that is opened or closed by a valve. Accordingly, abrasives are prevented from being precipitated, and the slurry solution is uniformly supplied to the semiconductor wafer, to thereby enhance polishing uniformity.

Chemical mechanical polishing (CMP) apparatus and CMP method using the

Isolation regions for a semiconductor layer of a semiconductor-on-insulator substrate are fabricated by forming a patterned implantation mask on the semiconductor layer. The patterned implantation mask includes mask sidewalls. An implantation masking film is formed on the sidewalls of the patterned implantation mask. Ions are implanted into the semiconductor layer, using the patterned implantation layer and the implantation masking film as a mask, to thereby form a doped region in the semiconductor layer. Sidewall spacers are formed on the implantation masking film, opposite the patterned implantation mask. The doped region between the sidewall spacers is etched to thereby define a trench in the semiconductor layer between the sidewall spacers and a doped edge layer in the semiconductor layer which extends from the trench to the implantation masking film. Insulating material is then formed in the trench.

Growing community of inventors

Yongin-si, South Korea

Joon-hee Lee