Samsung Electronics Co., Ltd.

Joo-young Lee

Ki-nam Kim

Do-hyung Kim

Young-so Park

Kyu-pil Lee

Young-hun Yu

Young-soh Park

A semiconductor memory device having an improved step profile between a cell array region and peripheral circuit region, and a method for manufacturing the same, are provided. The semiconductor memory device has a cell array region and a peripheral circuit region surrounding the cell array region. The cell array region includes a plurality of cell capacitors each of which comprises a cell storage electrode and a plate electrode, and a plurality of dummy cell capacitors each of which comprises a dummy storage electrode and a plate electrode. The dummy cell capacitors are formed at the edges of the cell array region. The outermost sidewall of each dummy storage electrode, facing toward the peripheral circuit region, has an inclined profile.

Semiconductor memory device having a capacitor over bit-line structure and method for manufacturing the same

Semiconductor memory device having a capacitor over bitline structure and method for manufacturing the same

An integrated circuit device includes a substrate, an insulating layer on the substrate, and a plurality of parallel conductive lines on the insulating layer. An etch barrier is on each of the parallel conductive lines wherein each of the etch barriers comprises a layer of silicon nitride on a respective conductive line and wherein each of the etch barriers further comprises a layer of silicon on the silicon nitride layer. In addition, the device includes a plurality of conductive vias through the insulating layer providing electrical connection to respective surface portions of the substrate, wherein each of the conductive vias is provided in the insulating layer between the etch barriers.

Methods for fabricating integrated circuit devices including etching

Integrated circuit memory devices are fabricated by forming a first contact hole in a cell array region and a second contact hole in a peripheral circuit region. Conductive material is simultaneously placed in the first and second contact holes such that the conductive material in the first contact hole electrically contacts a memory cell transistor in the cell array region and the conductive material in the second contact hole electrically contacts the peripheral circuit transistor in the peripheral circuit region. A capping layer is included, and the peripheral circuit region wiring layer and the capacitor storage electrode is formed directly on the capping layer. Improved performance and reduced step height may thereby be obtained.

Fabricating methods including capacitors on capping layer

A second insulating layer is used to mask a first insulating layer on a second gate electrode, during fabrication of a conductive contact adjacent a first gate electrode which is spaced apart from the second gate electrode. By using the second insulating layer as a sacrificial insulating layer during etching of the conductive contact, thinning of the first insulating layer on the second gate electrode may be prevented. In particular, first and second spaced apart gate electrodes are formed on an integrated circuit surface. The first and second spaced apart gate electrodes include first and second sidewalls, respectively. The first insulating layer and the second insulating layer are formed on the integrated circuit surface, including on the first and second gate electrodes. The second insulating layer is removed from the first gate. The first insulating layer is etched on the first gate to thereby form first spacers on the first sidewalls. A conductive contact is formed on the integrated circuit face, adjacent the first gate electrode and extending onto the first sidewall. The second insulating layer is removed from on the second gate and the first insulating layer is etched on the second gate, to thereby form second spacers on the second sidewalls.

Dual insulating layer methods for forming integrated circuit gates and

A contact site is formed for contacting a substrate adjacent an electrode formed on the substrate, the electrode and the substrate being separated by a first insulating layer formed on the substrate, the electrode having a top surface and a sidewall surface. A second insulating layer is formed which covers the top and sidewall surfaces of the electrode. A dielectric region is then formed on the second insulating layer, overlying the electrode and disposed adjacent an exposed portion of the second insulating layer which overlies a portion of the microelectronic layer laterally adjacent the electrode, the dielectric region having a sidewall surface adjacent the exposed portion of the second insulating layer. A third insulating layer is formed which covers the exposed portion of the second insulating layer and the sidewall surface of the dielectric region. Portions of the first, second and third insulating layers are then removed to expose a portion of the substrate adjacent the electrode while leaving the electrode covered. The dielectric region may be formed by forming an etching stop layer on the second insulating layer, forming a dielectric layer on the etching stop layer, and removing portions of the dielectric layer and the etching stop layer to expose a portion of the second insulating layer overlying a portion of the microelectronic layer laterally adjacent the electrode and to form a dielectric region and an etching stop region adjacent the exposed portion of the second insulating layer, the dielectric region and the etching stop regions having respective sidewall surfaces adjacent the exposed portion of the second insulating layer. The third insulating layer may be formed to cover the exposed portion of the second insulating layer and the sidewall surfaces of the dielectric and etching stop regions.

Method of fabricating contact sites for microelectronic devices

Intergrated circuit memory devices including capacitors on capping layer

A method of projection exposure utilizing a mask including a step of exposing an object by utilizing a transparent mask substrate of which the upper surface is slanted at a predetermined angle from a direction perpendicular to the light path and an opaque film pattern is formed at regular intervals on a lower surface of the mask substrate so that the phase difference between adjacent mask patterns occurs due to the slanted mask substrate, thereby reducing the minimum pitch available for pattern formation without a shorter-wavelength light source and without increasing NA by reducing the frequency difference .delta.v to the pitch d of the mask in a given wavelength of a light source and NA.

Projection exposure method and mask employed therein

A method for fabricating an integrated circuit device includes the steps of forming an insulating layer on a substrate and forming a plurality of parallel conductive lines on the insulating layer. An etch barrier is formed on each of the parallel conductive lines, and contact holes are formed between the etch barriers. The contact holes expose portions of the substrate without exposing the plurality of parallel conductive lines. In particular, the contact holes can be formed by forming a patterned mask layer on the insulating layer and etch barriers, and etching exposed portions of the insulating layer. The patterned mask layer selectively exposes a plurality of parallel strips orthogonal to the plurality of parallel conductive lines. Related structures are also discussed.

A capacitor of a semiconductor device has a plate electrode which process margin and a method of manufacturing same are disclosed. The plate electrode has a planarized surface and borders a source region. A recessed field oxide layer defining an active region is formed on a semiconductor substrate. Then, an insulating pattern for self-aligning an electrode is formed on the active region. The insulating pattern has a step with respect to the field oxide layer. Thereafter, a trench is formed in the semiconductor substrate by partially removing the field oxide layer, the insulating pattern and a surface portion of the semiconductor substrate. A conductive material is deposited on the semiconductor substrate having the trench and the insulating pattern to form a conductive layer filling the trench. Then, the conductive layer is polished until the insulating pattern is exposed, to thereby obtain an electrode having a planarized surface. The plate electrode does not unnecessarily occupy space of the active region and the plate electrode bordering the active region can be formed by self-alignment with a step between the insulating pattern and the field oxide layer. Therefore, sufficient process margin is provided to generate high yields, and a highly integrated semiconductor device having an AST cell can be realized.

Growing community of inventors

Kyungki-do, South Korea

Joo-young Lee