Samsung Electronics Co., Ltd.

Skhynix Inc.

Samsung Display Co., Ltd.

Korea Advanced Institute of Science and Technology

Samsung Sds Co., Ltd.

Joo-Young Lee

Jung-Suk Han

Jong-Seo Lee

Won-Il Lee

Tae-Jong Jun

Hoe-Seung Jung

Yong-kwan Kim

Duk-Jae Moon

Seong-Sik Shin

Se-keun Park

Nam-Jin Jang

Jin-a Kim

Dong-Gun Park

Jin-Woo Lee

Cha-Won Koh

Kyu-Young Choi

Yeong-Cheol Lee

Seung-Mock Ro

Jin-Seok Jang

Ki-Nam Kim

Jinwon Kim

Ji-Hwan Jang

Tae-young Chung

Young-Min You

Soo-Lin Kim

Jonguk Bang

Jung-Woo Song

Ji-Hoon Kwon

Yong Jik Park

Sun Hyang Song

Myeong-An Min

Myoung Hee Lee

Woo-Young Cheon

A method of generating a cryptographic algorithm according to one embodiment of the present disclosure includes generating one or more key tables on the basis of a seed value; generating a first transformation function that converts an input bit string, which is input to one of input branches of a Feistel structure, into a first random bit string having a length that extends beyond a length of the input bit string; generating a second transformation function that converts a second random bit string generated by referencing the one or more key tables into a third random bit string having a length that is the same as the length of the input bit string; and generating a block cryptographic algorithm of a Feistel structure which includes a round function to which the one or more key tables, the first transformation function, and the second transformation function are applied.

Apparatus and method for generating cryptographic algorithm, apparatus and method for encryption

A method of generating a cryptographic algorithm includes generating at least one key table on the basis of a seed value; generating, by using a round tweak bit string and an input bit string that is input to one of input branches of a Feistel structure, a first transformation function converting the input bit string into a first random bit string having a length that extends beyond a length of the input bit string, generating a second transformation function converting a second random bit string generated by referencing the one or more key tables into a third random bit string having a length that is the same as the length of the input bit string, and generating a block cryptographic algorithm of a Feistel structure which includes a round function to which the one or more key tables, the first transformation function, and the second transformation function are applied.

A method for operating a memory system including a memory device and a controller which controls the memory device includes identifying a target command among a plurality of commands queued in a host command queue; comparing an estimated power with a power limit; checking an estimated de-queuing time in the case where the estimated power is larger than or equal to the power limit; dequeuing the target command from the host command queue to a memory command queue in the case where the estimated de-queuing time is smaller than a predetermined threshold value; de-queueing the target command from the memory command queue to the memory device; and performing an operation corresponding to the target command.

Memory system and operating method thereof

A memory system includes: a memory device; a first queue suitable for queuing commands received from a host; a second queue suitable for enqueuing the commands from the first queue and dequeuing the commands to the memory device according to the FIFO scheme; and a processor suitable for: delaying enqueuing a read command into the second queue until the program operation is successfully performed when a logical address of a write command, in response to which a program operation is being performed, is the same as a logical address corresponding to the read command enqueued in the first queue; and determining whether or not to enqueue a subsequent read command, which is enqueued in the first queue after the read command, into the second queue.

A memory system includes: a memory device; a command queue queuing a program descriptor and a first read descriptor, and sequentially outputting the descriptors; a program manager performing an error handling operation in response to the program descriptor, the error handling operation including performing a program operation on a second physical address when a program operation performed on a first physical address fails; a fail managing buffer storing the first physical address for the failed program operation; a queue manager deleting the first read descriptor from the command queue and outputting an exception signal, when a physical address of the first read descriptor is the same as the first physical address; and a descriptor generator generating a second read descriptor including the second physical address in response to the exception signal and enqueuing the second read descriptor in the command queue, when the error handling operation passed.

A method according to one embodiment includes generating one or more key tables based on a first seed value; generating one or more secret values from a tweak value based on the one or more key tables; and performing encryption or decryption using the one or more secret values. An apparatus according to one embodiment includes a key table generator configured to generate one or more key tables based on a first seed value, a secret value generator configured to generate one or more secret values from a tweak value based on the one or more key tables, and an encryptor/decryptor configured to perform encryption or decryption using the one or more secret values.

Apparatus and method for encryption and decryption based on tweak converter to which key table is applied

A memory system includes: a memory device; a host interface suitable for receiving write commands and queueing the received write commands in an interface queue; a workload manager suitable for detecting, in a cache program mode, a mixed workload when a read count is greater than a first threshold value, the read count representing a number of read commands queued in the interface queue and the mixed workload representing receipt of a mix of read and write commands; a mode manager suitable for switching from the cache program mode to a normal program mode when the mixed workload is detected; and a processor suitable for processing write commands queued in a command queue in the cache program mode and processing write commands queued in the interface queue in the normal program mode when the mixed workload is detected.

Memory system with program mode switching based on mixed and sequential workloads

An imaging apparatus an image sensor which generates a reference image data of a reference area that includes a measuring area in which a display panel is positioned and an image processor which determines the measuring area by analyzing luminance of the reference image data and generates a crop image data that includes a measuring image data of the measuring area.

Imaging apparatus and driving method of the same

A controller configured to control memory chips in communication with the controller is provided. The controller comprises: a host interface configured to receive a request from a host; an address mapper configured to, upon receipt of both a turbo write request for writing data to one or more high-speed storage blocks at a high speed to and a normal write request for writing data to one or more storage blocks at a lower speed, allocate a first plane including a memory block configured to perform write operations in a single level cell mode at the high speed to a first plane group in order to respond to the turbo write request, and allocate a second plane to a second plane group at the slower speed in order to respond to the normal write request; and a memory interface configured to control the memory chips.

Controller and operation method thereof

A data processing system comprising: a host; and a memory system comprising a nonvolatile memory device and a controller suitable for controlling the nonvolatile memory device, wherein the controller comprises: a first reset circuitry suitable for loading firmware from the nonvolatile memory device to a volatile memory, and setting a reset default status; a second reset circuitry suitable for determining whether a reason for a reset request coincides with the reset default status, when the reset request is received from the host, and resetting the memory system; and a firmware load determination circuitry suitable for determining whether to reload the firmware by checking the reset default status.

Memory system, data processing system and operating method thereof

A semiconductor device includes a bit line structure on a substrate, a spacer structure including a first spacer directly contacting a sidewall of the bit line structure, a second spacer directly contacting a portion of an outer sidewall of the first spacer, the second spacer including air, and a third spacer directly contacting an upper portion of the first spacer and covering an outer sidewall and an upper surface of the second spacer, and a contact plug structure extending in a vertical direction substantially perpendicular to an upper surface of the substrate and directly contacting an outer sidewall of the third spacer at least at a height between respective heights of a bottom and a top surface of the second spacer.

Semiconductor device having bit line structure with spacer structure and method of manufacturing the same

A memory system includes: a memory device including a memory block, a page buffer, and first and second memory dies; a write buffer suitable for temporarily storing first and second data; a program managing unit suitable for controlling the memory device to sequentially perform first and second program operations on the memory block with the first and second data; a buffer managing unit suitable for managing the write buffer based on a scatter-gather scheme; a failure processing unit suitable for forcing the second program operation to fail, when the first program operation is a failure; and an error handling unit suitable for controlling the program managing unit to perform the first and second program operations again for the first and second data that are temporarily stored in the write buffer when the second program operation is forced to fail.

Operating method forcing the second operation to fail using a scatter-gather buffer and memory system thereof

A memory system includes: a memory device including a first memory buffer and a second memory buffer; a controller write buffer; a memory buffer manager suitable for controlling the memory device to buffer first data stored in the first memory buffer into the second memory buffer while the memory device programs, in a program operation, the first data into a memory block; a controller buffer manager suitable for deleting the first data stored in the controller write buffer after the memory device buffers the first data into the second memory buffer; and a failure processor suitable for controlling the memory device to perform a reprogram operation of reprogramming the first data, when the program operation fails.

A memory system includes a memory device; a short super block detecting unit suitable for forming, when one or more initial bad blocks remain in an original super block after a re-mapping operation is performed and a number of the initial bad blocks is equal to or less than a predetermined threshold value within the original super block, a short super block with memory blocks included in the original super block; a bitmap generating unit suitable for generating a bitmap representing whether each of the memory blocks included in the short super block is a normal block or an initial bad block; and a processor suitable for controlling the memory device to simultaneously perform a normal operation on normal blocks among the memory blocks included in the short super block based on the bitmap.

A method for operating a memory system which includes a memory device and a controller for controlling the memory device, the operating method includes searching one or more open memory blocks included in the memory device, when a booting operation is performed; detecting one or more erase pages included in each of the open memory blocks; checking an erase threshold voltage distribution corresponding to each of the erase pages; counting a number of first bad pages among the erased pages based on the erase threshold voltage distribution; and switching a first open memory block including the first bad pages among the open memory blocks into a first closed memory block when the number of first bad pages is equal to or greater than a first threshold value.

Growing community of inventors

Seoul, South Korea

Joo-Young Lee