Altera Corporation

Joo Ming Too

Kar Keng Chua

Chooi Pei Lim

Yew Fatt Kok

Kok Yoong Foo

Yew Fatt (Edwin) Kok

Tze Haw Liew

Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.

Clock signal networks for structured ASIC devices

Circuits, methods, and apparatus that provide the improvement or recovery of a duty cycle of a clock signal. One embodiment of the present invention receives a clock signal that may have a degraded duty cycle. The frequency of the clock signal is divided by two. The frequency-divided signal is delayed in order to generate two signals that are phase shifted from one another by 90 degrees. These signals are then exclusive-ORed together to generate a recovered clock. A control loop is provided to adjust the phase shift between the signals to be approximately 90 degrees.

Clock duty cycle recovery circuit

Growing community of inventors

Kedah, Malaysia

Joo Ming Too