Samsung Electronics Co., Ltd.

Joo Hee Jang

Pil-Kyu Kang

Byung Lyul Park

Jin Ho An

Seokho Kim

Taeyeong Kim

Jae Hyung Park

Hoon Joo Na

Seok Ho Kim

Kwang Jin Moon

Kyu Ha Lee

Hyoju Kim

A method for wafer planarization includes forming a second insulating layer and a polishing layer on a substrate having a chip region and a scribe lane region; forming a first through-hole in the polishing layer in the chip region and the scribe lane region and a second through-hole in the second insulating layer in the chip region, wherein the second through-hole and the first through-hole meet in the chip region; forming a pad metal layer inside the first through-hole and the second through-hole and on an upper surface of the polishing layer; and polishing the polishing layer and the pad metal layer by a chemical mechanical polishing (CMP) process to expose an upper surface of the second insulating layer in the chip region and the scribe lane region.

Method for wafer planarization and an image sensor made by the same

Semiconductor devices having stacked structures and methods for fabricating the same are provided. A semiconductor device includes at least one single block including a first semiconductor chip and a second semiconductor chip stacked thereon. Each of the first and second semiconductor chips includes a semiconductor substrate including a through-electrode, a circuit layer on a front surface of the semiconductor substrate, and a front pad that is provided in the circuit layer and is electrically connected to the through-electrode. The surfaces of the semiconductor substrates face each other. The circuit layers directly contact each other such that the semiconductor chips are bonded to each other.

Semiconductor devices having stacked structures and methods for fabricating the same

Growing community of inventors

Hwaseong-si, South Korea

Joo Hee Jang