Samsung Electronics Co., Ltd.

Joo-chan Kim

Jin-Woo Kim

Chul-soon Kwon

Yong-hee Kim

Eui-Youl Ryu

Dai-geun Kim

Jae-Hyun Park

Sang-Wook Park

Jae-Min Yu

Don-Woo Lee

Kook-Min Kim

Richard Anthony Conti

Zhao Lun

Johnny Widodo

William C Wille

Jae-eon Park

Jun-jung Kim

Dae-geun Kim

Eui-youl Ryu

Biao Zuo

Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5&#xd7;10ions/cm. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.

Methods of forming integrated circuit devices having ion-cured electrically insulating layers therein

A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.

Flash memory device having a split gate

A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.

Semiconductor device having a measuring pattern and a method of measuring the semiconductor device using the measuring pattern

Flash memory device having a split gate and method of manufacturing the same

A method of manufacturing split-gate memory provides a control gate insulating film and the tunneling insulating film in a cell region, a high voltage gate insulating film in a high voltage region, and a low voltage gate insulating film in a low voltage region, all having different thickness. Additionally, a pre-cleaning process removes an outer sidewall portion of a spacer to form a tip portion of a floating gate that overlaps a control gate line formed proximate the floating gate.

Method of manufacturing split-gate memory

Growing community of inventors

Seoul, South Korea

Joo-chan Kim