Duke University

Synopsys, Inc.

Jonti Talukdar

Krishnendu Chakrabarty

Arjun Chaudhuri

Mayukh Bhattacharya

Shan Yuan

Huiping Huang

A method of determining defect sensitization includes parsing a netlist of a circuit design to determine a plurality of potential defects and partitioning the circuit design into a plurality of blocks. The method also includes generating a graph representing the circuit design and determining a transitive closure of the graph. The method further includes grouping the plurality of potential defects to produce a plurality of groups of potential defects and selecting a potential defect from each group of the plurality of groups to form a simulation group of potential defects. The method also includes simulating the circuit design by injecting, into the circuit design, every potential defect of the simulation group to produce a set of outputs of the plurality of blocks and determining a defect sensitization for the simulation group of potential defects based on the set of outputs of the plurality of blocks.

Measuring device defect sensitization in transistor-level circuits

An integrated circuit (IC) protection circuit can include a reconfigurable block that receives a seed value from a tamper-proof memory and generates a dynamic key; an authentication block that receives the dynamic key from the reconfigurable block and taint bits from a scan chain to generate an authentication signature; and an encryptor that encrypts a test pattern response on the scan chain if a mismatch is found between the authentication signature and a test pattern embedded signature.

Dynamic scan obfuscation for integrated circuit protections

An integrated circuit (IC) protection circuit for an IC includes a controller with a barrier finite state machine (FSM) having a key sequence input that unlocks the controller; and a signal scrambler coupled to receive at least two initialization inputs and a primary input path and output a signal to the IC, wherein at least one initialization input of the at least two initialization inputs is based on an output of the barrier FSM. The IC protection circuit can further include a dynamic authentication circuit coupled to receive the output of the barrier finite state machine and output a signal to the signal scrambler for one of the at least two initialization inputs. The dynamic authentication circuit can be formed of a dynamic sequence generator and a dynamic sequence authenticator, each formed of one or more reconfigurable linear feedback shift registers, and a comparator.

Integrated circuit protections against removal and oracle-guided attacks

A system for evaluating fault criticality using machine learning includes a first machine learning module that is trained on a subset of a circuit and used for evaluating whether a node in a netlist of the entire circuit is a critical node, and a second machine learning module specialized to minimize classification errors in nodes predicted as benign. A generative adversarial network can be used to generate synthetic test escape data to supplement data used to train the second machine learning module.

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Durham, NC, United States of America

Jonti Talukdar