Samsung Electronics Co., Ltd.

Jongwon Hong

Jongmin Baek

Gilheyun Choi

Jongmyeong Lee

Hei Seung Kim

Kyu-Hee Han

Jang-Hee Lee

Insun Park

GeumJung Seong

Hyunbae Lee

Bonghyun Choi

Jung-soo Yoon

Minjong Kim

Soyoung Lee

Ik Soo Kim

Suho Lee

Kyoung-Hee Kim

Ho-Ki Lee

Juhyun Lee

Chang-yun Lee

Kyoung Hee Nam

Jaebeom Park

Keeyoung Jun

Choongrae Cho

Seonggil Park

Disclosed is a substrate processing apparatus. The substrate processing apparatus comprises a process chamber providing an inner space where a substrate is treated, a support unit disposed in the inner space and supporting the substrate, and a gas supply unit providing the inner space with a process gas required for generating plasma. The support unit comprises a base having a top surface on which the substrate is placed, a heater disposed in the base, and a coating layer formed on the top surface of the base.

Substrate processing apparatus

A deposition apparatus includes a chuck in a process chamber, the chuck having a top surface on which a substrate is loaded, a showerhead disposed over the chuck, and a fence extension disposed in the process chamber. Plasma is generated in a space between the showerhead and the loaded substrate during a deposition process. The fence extension at least partially confines the plasma in the space during the deposition process, thereby enabling improved thickness uniformity and reliability of a layer deposited on the loaded substrate during the deposition process.

Plasma-enhanced chemical vapor deposition (PE-CVD) apparatus and method of operating the same

A substrate treating apparatus includes a chamber that encloses an internal space; a susceptor in a lower part of the internal space; a shower head in an upper part of the internal space and spaced above the susceptor and that includes a plurality of distribution holes; and a blocker plate assembly that comprises a body having a plurality of intake holes that divides a space between a top wall of the chamber and the shower head into an upper intake space and a lower distribution space, a ring-shaped partition rib on an upper surface of the body, and a ring-shaped distribution unit on a lower surface of the body.

Substrate treating apparatus and blocker plate assembly

Semiconductor devices, and methods of fabricating the same, include first conductive lines on a substrate, and a first molding layer covering the first conductive lines. The first conductive lines have air gaps between adjacent first conductive lines. Sidewalls of the first conductive lines and a bottom surface of the first molding layer collectively define a first gap region of each of the air gaps. The sidewalls of the first conductive lines and a top surface of the first molding layer collectively define a second air gap region of each of the air gaps.

Semiconductor devices and methods of fabricating the same

Semiconductor devices are provided. The semiconductor devices may include a non-planar conductive pattern. The non-planar conductive pattern may be on an insulating layer and may contact a connection terminal at a plurality of different heights. Related methods of forming semiconductor devices are also provided.

Semiconductor devices including a non-planar conductive pattern, and methods of forming semiconductor devices including a non-planar conductive pattern

Provided are methods of fabricating a semiconductor device and semiconductor devices fabricated thereby. In the methods, dummy recess regions may be formed between cell recess regions and a peripheral circuit region. Due to the presence of the dummy recess regions, it may be possible to reduce a concentration gradient of a suppressor contained in a plating solution near the dummy pattern region, to make the concentration of the suppressor more uniform in the cell pattern region, and to supply an electric current more effectively to the cell pattern region. As a result, a plating layer can be more uniformly formed in the cell pattern region, without void formation therein.

Electroplating methods for fabricating integrated circuit devices and devices fabricated thereby

A semiconductor device can include wiring lines on a substrate and an interlayer insulating structure, between ones of the wiring lines. The wiring lines can include a pore-containing layer that includes a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines.

Semiconductor devices

In a semiconductor device and a method of forming the same, the semiconductor device comprises: a first insulating layer on an underlying contact region of the semiconductor device, the first insulating layer having an upper surface; a first conductive pattern in a first opening through the first insulating layer, an upper portion of the first conductive pattern being of a first width, an upper surface of the first conductive pattern being recessed relative to the upper surface of the first insulating layer so that the upper surface of the first conductive pattern has a height relative to the underlying contact region that is less than a height of the upper surface of the first insulating layer relative to the underlying contact region; and a second conductive pattern contacting the upper surface of the first conductive pattern, a lower portion of the second conductive pattern being of a second width that is less than the first width.

Semiconductor devices including interlayer conductive contacts and methods of forming the same

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Hwaseong-si, South Korea

Jongwon Hong