Korea University Research and Business Foundation

Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Skhynix Inc.

Agency for Defense Development

Jongsun Park

Woong Il Choi

Kyeongho Lee

Gyuseong Kang

Taehwan Kim

Taejoong Song

Joonhyung Kim

Wonseok Choi

Hyunjun Kim

Sunin Jeong

Kyung Jin Lee

Yongkon Kim

Woojin Rim

Seonggeon Park

Gyuhong Kim

Dong Yeob Shin

Munseon Jang

Hyunchul Park

Dongsu Kim

Hoyoung Tang

Jinseok Choi

Dongyeob Shin

Joo Yoon Kim

Kyeong-ho Lee

Minseo Kim

Hyunbok Park

Chaehyeon Shin

Jinmo Kwon

Geon Ko

Bohun Kim

Kyeong Ho Lee

Junghak Ryu

Jinho Jeong

Kangsan Lee

Donghwa Kim

Myungkil Ahn

Kwanghyo Jeong

Yunho Jang

Jin-Il Chung

Sung Soo Cheon

Disclosed is a field programmable gate array device including a plurality of lookup tables each storing data. Each lookup table includes a cell array including cells connected to a plurality of word lines, a drive circuit connected to the cell array through the plurality of word lines, and a peripheral circuit connected to the cell array through a plurality of bit lines and source lines, and configured to control the drive circuit. The drive circuit drives a first word line among the word lines based on first input signals. The peripheral circuit performs a data write operation on a first cell connected to the first word line, based on a first command and a second input signal, and performs a data read operation on the first cell connected to the first word line, based on a second command and the second input signal.

Field programmable gate array device including spin orbit torque-magnetic random access memory and operating method thereof

A coding circuit includes an encoder circuit that generates parity by applying input data to a parity generating matrix and generate input codeword by concatenating the input data and the parity, and a decoder circuit that detects and corrects an out-of-boundary 2-bit error using syndromes. The out-of-boundary 2-bit error corresponds to two 1-bit errors occurred at two symbols respectively among a plurality of symbols included in output codeword, and the syndromes are generated by applying the output codeword to the parity generating matrix.

Coding circuit and memory device including the same

Disclosed is a method of reading a nonvolatile resistive memory device including a data cell and a reference cell. The method includes precharging a first bit line connected to the data cell and a second bit line connected to the reference cell, discharging a voltage precharged to the first bit line and the second bit line to a source node through the data cell and the reference cell, sampling a reference voltage developed to the second bit line at a first time when a voltage of the first bit line reaches a threshold voltage, sampling a data voltage developed to the first bit line at a second time when a voltage of the second bit line reaches the threshold voltage, and sensing and amplifying a difference value between the reference voltage and the data voltage and outputting the sensed and amplified difference value as output data.

Nonvolatile resistive memory device using dynamic reference in dual domain and read method thereof

A physically unclonable function magnetic memory device includes a plurality of magnetic resistance cells disposed on a substrate and each including a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer or a non-magnetic conductive layer interposed between the pinned magnetic layer and the free magnetic layer. In an operating method of the physically unclonable magnetic memory device, an external magnetic field, decaying with time, is applied to the plurality of magnetic resistance cells to randomize a magnetization direction of the free magnetic layer of each of the plurality of magnetic resistance cells.

Operating method of physically unclonable function magnetic memory device

An SRAM cell includes a first pass gate transistor connected with a first word-line and a local bit-line, a first inverter that includes an output terminal connected with the first pass gate transistor and an input terminal, a second inverter that includes an input terminal connected with the first pass gate transistor and an output terminal, a second pass gate transistor connected with a second word line, the input terminal of the first inverter and the output terminal of the second inverter, and a complementary local bit-line, a first transistor connected with the second pass gate transistor, a local computing line, and a ground electrode, and a second transistor connected with a third word-line, the local computing line, and the ground electrode.

SRAM cell configured to perform multiply-accumulate (MAC) operation on multi-bit data based on charge sharing and method of operating the same

Disclosed is a computing-in-memory device, which includes a memory cell array including an analog multiplication unit that performs a multiply-accumulate (MAC) operation on a pre-stored weight and a first analog voltage corresponding to multi-bit input data, and a driver that applies the multi-bit input data to the analog multiplication unit, and the analog multiplication unit includes a digital-to-analog converter that converts the multi-bit input data into the first analog voltage.

Computing-in-memory device including digital-to-analog converter based on memory structure

A coding circuit includes an encoder circuit configured to generate an input codeword by concatenating an input data and a parity generated by processing the input data using an odd parity generator matrix; and a decoder circuit configured to correct a double error from an output codeword, and to detect a triple error using a syndrome generated by processing the output codeword using the odd parity generator matrix, wherein each column of the odd parity generator matrix has a respective odd number of 1's.

Embodiments of the present disclosure provide a spin orbit torque device-based processing-in-memory device that includes a digital logic gate using a current switching and voltage controlled magnetic anisotropy (VCMA) effect of a spin orbit torque device capable of being used as a memory element, and increases the overall system energy efficiency by designing a memory capable of performing an MAC operation to reduce the number of data migration between a memory and an operator.

Processing-in-memory device based on spin orbit torque device

Embodiments of the present disclosure described herein relate to a computing in memory electronic device that supports current based analog operations and time based analog-to-digital conversion.

Computing in memory electronic device capable of supporting current based analog multiply-accumulation operations and time based analog-to-digital conversion

A memory device includes a memory cell array connected to a first word line, a pair of second word lines, and a bit line and configured to perform a multiply-accumulate (MAC) operation depending on a ternary input provided from the pair of second word lines and a binary weight preset based on the first word line and the bit line; a peripheral circuit configured to control the memory cell array; and an ADC (analog-to-digital converter) circuit configured to convert a voltage value dependent on the MAC operation into a digital value.

Memory device supporting in-memory MAC operation between ternary input data and binary weight using charge sharing method and operation method thereof

A deep neural network accelerator includes a unit array including a first sub-array including a first operational unit and a second sub-array including a second operational unit. The first and second operational units have different sizes from each other, the sizes of the first and second operational units are in proportion to each cumulative importance value accumulated in each operational unit of the unit array while performing a deep neural network operation, and the each cumulative importance value is obtained by accumulating an importance for each weight mapped to the each operational unit of the unit array.

Deep neural network accelerator using heterogeneous multiply-accumulate unit

An in-memory computing device includes a memory cell array and a column peripheral circuit including a plurality of column peripheral units connected to a plurality of pairs of bit lines connected to the memory cell array. Each of the column peripheral units includes a sense amplifying and writing unit sensing and amplifying bitwise data through one pair of bit lines among the pairs of bit lines and an arithmetic logic unit performing an arithmetic operation with a full adder Boolean equation based on the bitwise data and performing a write back operation on operation data obtained by the arithmetic operation via the sense amplifying and writing unit.

In-memory computing device supporting arithmetic operations

A computing in-memory device includes a memory cell array supporting a bitwise operation through at least one pair of memory cells activated in response to at least one pair of word line signals and a peripheral circuit connected to the at least one pair of memory cells via one pair of bit lines and performing a discharging operation on at least one bit line of the one pair of bit lines based on a voltage level of the one pair of bit lines.

Computing in-memory device supporting arithmetic operations and method of controlling the same

Disclosed are an artificial neural network device and a method of operating the same. The artificial neural network device includes an operation part performing an artificial neural network operation on an input feature map and a classification part performing a classifying operation on the input feature map based on the artificial neural network operation of the operation part. The operation part includes an XNOR operation circuit performing an XNOR operation on the input feature map and a filter and a binarizing circuit performing a binarization operation based on the result of the XNOR operation of the XNOR operation circuit. Accordingly, the artificial neural network device is miniaturized and performs the operation at high speed.

Processor in memory supporting binary convolution operation and method of operating the same

This application relates to a synchronization circuit for synchronizing signals used in a threshold implementation operation process performing in an S-box of an encryption circuit. In one aspect, the synchronization circuit includes an enable signal generator configured to generate an enable signal. The synchronization circuit may also include a synchronization unit included in an encryption circuit and located inside an S-box that performs a threshold implementation operation that calculates by dividing bits of an input signal into bits equal to or greater than the number of bits of the input signal. The synchronization unit may be configured to synchronize signals used in a threshold implementation operation process based on the generated enable signal.

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Seoul, South Korea

Jongsun Park