Samsung Electronics Co., Ltd.

Jongsoon Park

Jongchul Park

Jong-Kyu Kim

Yil-hyung Lee

Sang-Kuk Kim

Woohyun Lee

Hyeji Yoon

Inho Kim

Jeongyun Lee

Hyungjoon Kwon

Haegeon Jung

Bosoon Kim

Hyunggoo Lee

InWon Park

Bokyoung Lee

Yeondo Jung

A semiconductor device includes a substrate including a boundary region between first and second regions, first active patterns on the first region, second active patterns on the second region, and an isolation insulating pattern on the boundary region between the first and second active patterns. A width of at least some of the first active patterns have different widths. Widths of the second active patterns may be equal to each other. A bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to a corresponding first active pattern, a second bottom surface adjacent to a corresponding second active pattern, and a third bottom surface between the first bottom surface and the second bottom surface. The third bottom surface is located at a different height from those of the first and second bottom surfaces with respect to a bottom surface of the substrate.

Semiconductor devices including an isolation insulating pattern on a boundary region of a substrate and between first active patterns and second active patterns

A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch. The first distance may be about 0.8 times to about 1.2 times the first pitch.

Semiconductor devices and method of manufacturing the same

Semiconductor devices including an isolation insulating pattern with a first bottom surface, a second bottom surface, and a third bottom surface therebetween, where the third bottom surface has a different height than the first and second bottom surfaces

An ion beam apparatus may include a chamber assembly configured to hold a material and direct an ion beam on the material, a detector configured to detect a signal generated from the material based on the ion beam being directed on the material, and a controller configured to control at least one parameter associated with the chamber assembly based on the signal, such that at least one of an ion energy associated with the ion beam, an ion current associated with the ion beam, and an incident angle of the ion beam with respect to a top surface of the material is changed continuously with time.

Ion beam apparatus with continuously changing parameter control

An etching target layer is formed on a substrate. An upper mask layer is formed on the etching target layer. A plurality of preliminary mask patterns is formed on the upper mask layer. The plurality of preliminary mask patterns is arranged at a first pitch. Two neighboring preliminary mask patterns of the plurality of preliminary mask patterns define a preliminary opening. An ion beam etching process is performed on the upper mask layer using the plurality of preliminary mask patterns as an etch mask to form a first preliminary-interim-mask pattern and a pair of second preliminary-interim-mask patterns. The first preliminary-interim-mask pattern is formed between one of the pair of second preliminary-interim-mask patterns and the other of the pair of second preliminary-interim-mask patterns.

Methods of fabricating semiconductor device

A method of forming fine patterns includes forming an upper mask layer on a substrate, forming preliminary mask patterns on the upper mask layer, and forming upper mask patterns by etching the upper mask layer using the preliminary mask patterns as etch masks. Forming the upper mask patterns includes etching the upper mask layer by performing an etching process using an ion beam. The upper mask patterns include a first upper mask pattern formed under each of the preliminary mask patterns, and a second upper mask pattern formed between the preliminary mask patterns in a plan view and spaced apart from the first upper mask pattern.

Method of forming fine patterns of a semiconductor device

Ion beam apparatuses and methods for forming patterns using the same, and methods for manufacturing magnetic memory devices using the same

A semiconductor memory device that includes at least a lower contact plug on a semiconductor substrate, a magnetic tunnel junction of the lower contact plug, and a barrier pattern on a sidewall of the lower contact plug may further include an insulation pattern on the sidewall of the lower contact plug. The insulation pattern may be between the barrier pattern and the magnetic tunnel junction pattern. The insulation pattern may include an upper portion and a lower portion whose width is greater than a width of the upper portion.

Semiconductor memory device

Data storage devices are provided. A data storage device includes a dielectric layer on a substrate. The data storage device includes a plurality of data storage structures on the dielectric layer. The data storage device includes a conductive material on the dielectric layer. Moreover, the data storage device includes an insulation layer on the conductive material.

Data storage devices

A patterning method includes forming an etch-target layer on a substrate, forming mask patterns on the etch-target layer, and etching the etch-target layer using the mask patterns as an etch mask to form patterns spaced apart from each other. The etching process of the etch-target layer includes irradiating the etch-target layer with an ion beam, whose incident energy ranges from 600 eV to 10 keV. A recess region is formed in the etch-target layer between the mask patterns, and the ion beam is incident onto a bottom surface of the recess region at a first angle with respect to a top surface of the substrate and is incident onto an inner side surface of the recess region at a second angle with respect to the inner side surface of the recess region. The first angle ranges from 50&#xb0; to 90&#xb0; and the second angle ranges from 0&#xb0; to 40&#xb0;.

Growing community of inventors

Suwon-si, South Korea

Jongsoon Park