Omnivision Technologies, Inc.

Integrated Silicon Solution Incorporated

Jongsik Na

Taehyung Jung

Sunny Ng

Wing-Hin Kao

Multiport memory architecture is disclosed herein. An example memory includes an input port, a memory array, and an output port. The input port is coupled to receive data blocks and includes first and second buffers coupled to temporarily store alternate data blocks, and the output port is coupled to provide data blocks from the memory array. The memory array is partitioned into first and second partitions, with the first partition coupled to receive data blocks from the first buffer and the second partition coupled to receive data blocks from the second buffer, and the input port and the memory array are coupled to receive control signals to simultaneously receive a first data block at the first buffer, transfer a second data block from the second buffer to a first address in the second partition, and provide a third data block stored at a third address of the first partition.

Multiport memory architecture for simultaneous transfer

A dynamic random-access memory (DRAM) for use with a display includes a plurality of capacitive elements coupled to store one or more bits of data, and a plurality of switches where at least one individual switch in the plurality of switches is coupled to an individual capacitive element in the plurality of capacitive elements. A plurality of input/output (I/O) bit lines including 32 or more input/output bit lines is coupled to read out the data from the plurality of capacitive elements. A plurality of column select lines is coupled to enable readout of the plurality of capacitive elements.

DRAM core architecture with wide I/Os

A memory device using error correction code (ECC) implements a memory array parallel read-write method to reduce the storage overhead required for storing ECC check bits. The memory array parallel read-write method stores incoming address and data into serial-in parallel-out (SIPO) address registers and write data registers, respectively. The stored data are written to the memory cells in parallel when the SIPO registers are full. ECC check bits are generated for the block of parallel input data stored in the write data registers. During the read operation, a block of read out data corresponding to the read address are read from the memory cells in parallel and stored in read registers. ECC correction is performed on the block of read out data before the desired output data is selected for output.

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San Ramon, CA, United States of America

Jongsik Na