Samsung Electronics Co., Ltd.

Jongpil Son

Seongil O

Soojung Ryu

Kyomin Sohn

Sangoak Woo

Chankyung Kim

Hosung Song

Seungcheol Baek

Sanghyuk Kwon

Minyoung Son

Minkyu Jeong

Wooyeong Cho

Sangbeom Kang

Wonchang Jung

A memory device is provided. The memory device includes: a first memory cell array including a first row and a second row; and a self-refresh circuit configured to control refresh in response to a first self-refresh entry signal, and stop refresh of the second row after refreshing the first row in response to a self-refresh exit signal.

Memory device and refresh method thereof

A memory device includes a memory cell array and a repair circuit configured to perform a repair operation and output a dirty signal to an external destination external to the memory device. The repair circuit further performs selecting a first redundancy address of the redundancy memory cells instead of a first fail address of the first failed memory cell, storing a first redundancy mapping for the first fail address to the first redundancy address, and in response to determining a second fail address of a second failed memory cell matches the first fail address, ignoring the first redundancy mapping, and outputting a dirty signal causing a second redundancy mapping to map the first fail address to a second redundancy address different from the first redundancy address of the redundancy memory cells.

Memory device for outputting test results

Disclosed is a semiconductor memory device that includes a memory cell array including a plurality of memory banks, a command decoder configured to decode a per-bank refresh command and a remaining bank refresh command received from an external source, and a refresh controller configured to control the cell array to perform a per-bank refresh operation for refreshing one memory bank among the plurality of memory banks that is based on a decoding result of the per-bank refresh command of the command decoder, wherein the refresh controller is configured to perform a remaining bank refresh operation for refreshing remaining memory banks other than the one memory bank among the plurality of memory banks, in response to the remaining bank refresh command during one refresh cycle.

Semiconductor memory device for performing remaining bank refresh operation and refresh method thereof

A semiconductor device includes a semiconductor die having a peripheral region surrounding, a defect detection circuit in the peripheral region, the defect detection circuit arranged in an open conduction loop, the defect detection circuit comprising a plurality of latch circuits and a plurality of defect detection conduction paths, each defect detection conduction path of the plurality of defect detection conduction paths connecting two adjacent latch circuits of the plurality of latch circuits, and a test control circuitry configured to perform (a) a test write operation by transferring bits of an input data pattern in a forward direction of the open conduction loop to cause the plurality of latch circuits to store the bits of the input data pattern in the plurality of latch circuits, and (b) a test read operation by transferring bits stored in the plurality of latch circuits in a backward direction of the open conduction loop.

Semiconductor device including defect detection circuit and method of detecting defects in the same

A memory device including an interface circuit for data conversion according to different endian formats includes an interface circuit that performs data conversion with hardware in a data transfer path inside the memory device in accordance with a memory bank, a processing element (PE), and an endian format of a host device. The interface circuit is (i) between a memory physical layer interface (PHY) region and a serializer/deserializer (SERDES) region, (ii) between the SERDES region and the memory bank or the PE, (iii) between the SERDES region and a bank group input/output line coupled to a bank group including a number of memory banks, and (iv) between the PE and bank local input/output lines coupled to the memory bank.

Memory device including interface circuit for data conversion according to different endian formats

A memory module includes semiconductor memory devices mounted on a circuit board and a control device mounted on the circuit board. Each semiconductor memory device includes a memory cell array to store data. The control device receives a command and an access address from an external device and provides the command and the access address to the semiconductor memory devices. Each semiconductor memory device performs an address swapping operation to randomly swap a portion of bits of the access address to generate a swapped address in response to a power-up signal or a reset signal, and enables a respective target word-line from among word-lines in the memory cell array such that two or more of the semiconductor memory devices enable different target word-lines in response to the access address.

Memory modules and stacked memory devices

A memory module includes a plurality of memory devices each including a memory cell array, and a register clock driver connected to the memory devices. The register clock driver detects a row hammer address among row addresses corresponding to word lines of the memory cell array, converts a refresh command, among a plurality of refresh commands received from a memory controller for refreshing the memory cell array, to a row hammer refresh command, and transmits the row hammer refresh command and the row hammer address to each of the memory devices.

Memory module including register clock driver detecting address frequently accessed

A semiconductor memory device includes a semiconductor substrate having an active region of a first conductivity type defined by a device isolation layer, a first impurity region in the active region, an anti-fuse gate electrode on the semiconductor substrate and extending across the first impurity region, an anti-fuse gate dielectric layer between the anti-fuse gate electrode and the first impurity region, a selection gate electrode on the semiconductor substrate and extending across the active region, a selection gate dielectric layer between the selection gate electrode and the active region, and a second impurity region in the active region between the selection gate electrode and the anti-fuse gate electrode. The first and second impurity regions have impurities of a second conductivity type. The first impurity region has an impurity concentration less than the impurity concentration of the second impurity region.

Semiconductor memory devices

An operation method of a memory device which includes a plurality of memory cells connected to a plurality of word lines includes receiving a first activate command from an external device, receiving at least one operation command from the external device after the first activate command is received, receiving a precharge command after receiving the at least one operation command, and receiving a second activate command from the external device after the precharge command is received. When the at least one operation command does not include a write command, the second activate command is received after a first precharge reference time elapses from a time at which the precharge command is received. When the at least one operation command includes the write command, the second activate command is received after a second precharge reference time elapses from the time at which the precharge command is received.

Memory device and operation method thereof

A computing system includes a memory device comprising a memory array and an internal processor configured to perform a first sub pipeline of a graphics pipeline for tile-based rendering by using graphics data stored in the memory array, for offload processing of the first sub pipeline from a host processor; and the host processor configured to perform a second sub pipeline of the graphics pipeline by using a result of the first sub pipeline stored in the memory array.

Computing system and method of performing tile-based rendering of graphics pipeline

A memory apparatus including multiple buffers includes a memory controller configured to obtain memory allocation information based on a multi-write operation command, and a memory configured to store same graphics data in each of multiple buffers in a memory based on the memory allocation information.

Memory apparatus including multiple buffers and method of driving memory including multiple buffers

A memory device includes a memory cell array, a multiplexing circuit, and a control logic circuit. The memory cell array includes a first sub memory cell array, a second sub memory cell array, and a third sub memory cell array. The multiplexing circuit selects the first sub memory cell array, the second sub memory cell array, and the third sub memory cell array in a first mode of operation, and when the first sub memory cell array is defective in a second mode of operation, the multiplexing circuit selects the second sub memory cell array and the third sub memory cell array. The control logic circuit selects the first mode of operation or the second mode of operation. The control logic circuit controls the multiplexing circuit so that the first, second and third sub memory cell arrays are connected to input or output pads.

Memory device including extra capacity and stacked memory device including the same

A method includes outputting, at a processor, a command and an address to the memory module, receiving match/unmatch bits indicating results of comparing a tag corresponding to the address with tags stored in the memory module, from the memory module, determining, at the processor, a cache hit/miss from the match/unmatch bits by using majority voting, and outputting, at the processor, the determined cache hit/miss to the memory module.

Growing community of inventors

Seongnam-si, South Korea

Jongpil Son