Samsung Electronics Co., Ltd.

Jongmin Park

Do-Han Kim

Tae-Kyeong Ko

Kyoyeon Won

Sungup Moon

Kwanghee Lee

Deokho Seo

Cholmin Kim

Jiyong Lee

A semiconductor memory device for a hash solution includes a hashing logic block including a plurality of hashing logics configured to perform a hash function, a memory cell block including a plurality of memory cells, and an input/output (I/O) control structure configured to change a data interface between the hashing logic block and the memory cell block based on a characteristic of the hash function to be performed.

Semiconductor memory device for hash solution and method of driving the same

A memory system includes a nonvolatile memory electrically connected to a data bus, a DRAM electrically connected to the data bus, and a memory controller configured to drive the DRAM as a cache memory and the nonvolatile memory as a main memory and to synchronize data of a cache line with data of the nonvolatile memory in units of cache units based on a dirty flag. The DRAM is configured to load data of the cache line that caches data stored in the nonvolatile memory and to store the dirty flag, which indicates whether a cache unit is dirty, in units of cache units, where a size of each cache unit is smaller than a size of the cache line.

Memory system including DRAM cache and cache management method thereof

An interface device, including a plurality of interface circuits, wherein each interface circuit of the plurality of interface circuits includes a first switching element connected in series to a second switching element, and a first capacitor and a second capacitor connected to an output terminal to which the first switching element and the second switching element are connected; and a controller configured to determine a plurality of output signals corresponding to the plurality of interface circuits by controlling the first switching element and the second switching element, and configured to adjust a slew rate of the plurality of output signals by charging and discharging the first capacitor and the second capacitor.

Interface circuit and interface device

In a memory module including a memory device and a filter, the memory device operates with a clock of a reference frequency. The filter receives a multiplexed signal from a host and filters a signal of a frequency band from the multiplexed signal. The frequency band includes the reference frequency and the signal of the frequency band is provided to the memory device.

Growing community of inventors

Busan, South Korea

Jongmin Park