Promos Technologies, Inc

Mosel Vitelic Corporation

Jongmin Park

Li-Chun Li

The sequence in which the voltages (V, V, V, and V) applied to the source/drain regions (S and D), select gate (SG), and (if present) control gate (CG) of a floating-gate field-effect transistor () start to change value during a programming operation is controlled so as to avoid adjusting the transistor's programmable threshold voltage toward a programmed value when the transistor is intended to remain in the erased condition, i.e., not go into the programmed condition. With the voltage (V) at one source/drain region (S) changing from a nominal value to a programming value, the sequence entails causing the voltage (SG) at the select gate to start changing from a nominal value to a programming-enable value after the voltage at the other source/drain region (D) starts changing from a nominal value to a programming-inhibit value.

Technique for programming floating-gate transistor used in circuitry as flash EPROM

Nonvolatile memory cells () are connected to a bitline (BL). The bitline is also connected to a source/drain region () of a transistor (), a Y multiplexer transistor for example. This source/drain region is exposed to a higher voltage, and hence is made to have a higher junction breakdown voltage, than the other source/drain region () of the same transistor. A nonvolatile memory has a plurality of memory arrays (), a global decoder () and secondary decoders (). The selection signals provided by the global decoder to the secondary decoders for selecting the control gate lines () and the source lines () are carried by lines () running in the row direction. These signals are low voltage signals (between 0V and Vcc). The super high voltages are carried by lines () extending in the column direction to reduce noise injection into the control gate lines, source lines, and wordlines (), and to reduce the parasitic capacitance associated with the super high voltage lines. An integrated circuit has at least two memory arrays () with control gate lines (), source lines (), and wordlines (). A global decoder () and secondary decoders () select the control gate lines and the source lines. Each secondary decoder is located in an area spaced from the arrays. The control gate line and source line decoding circuits in each secondary decoder share a common area to reduce the memory size. Other features are also provided.

Nonvolatile memories with asymmetric transistors, nonvolatile memories with high voltage lines extending in the column direction, and nonvolatile memories with decoding circuits sharing a common area

In some embodiments, of the present invention, data are written to a plurality of nonvolatile memory cells (Q, Q) as follows. A data writing signal is supplied to one of the memory cells (Q) but not to both of the memory cells. Then data writing signals are supplied to both of the memory cells simultaneously.

Writing data to nonvolatile memory

An operation, typically an erasure operation, is performed on a floating-gate FET () whose components include a body region (BR) and a control-gate electrode (CG) above a floating-gate electrode (FG). A first body voltage (V) at a body node (N) is converted into a second body voltage (V) applied to the body region. A first control voltage (V) at a control node (N) is converted into a second control voltage (V) applied to the control-gate electrode. The two first voltages are placed at respective conditioning values such that the two second voltages cause the FET to be in a specified condition, typically an erased condition. The two first voltages are subsequently discharged with the body and control nodes electrically connected to each other at least as the discharging begins. The two first voltages thereby begin discharging largely simultaneously. This avoids FET damage.

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Fremont, CA, United States of America

Jongmin Park