Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Jongmin Baek

Wookyung You

Sanghoon Ahn

Sangho Rha

Naein Lee

Nae-in Lee

Kyu-Hee Han

Jangho Lee

Suhyun Bark

Byunghee Kim

Koungmin Ryu

Deokyoung Jung

Kyeongbeom Park

Vietha Nguyen

Sangshin Jang

Bumsoo Kim

Choonghoon Lee

Yoonkyung Choi

Jinchul Lee

Kyuhee Han

Yunrae Jo

Jongwon Hong

Junghoo Shin

YoungWoo Cho

Chadong Kim

Junghwan Chun

Gyeonggon Lee

Jiwon Kang

Jiyoung Kim

Insun Park

Donghyun Roh

Taehui Na

Gangseub Lee

Sowoon YooN

Byung-Kwon Cho

Hak-Sun Lee

Hei Seung Kim

Jongryul Kim

Songyi Han

Dueung Kim

Jiwon Yun

Taejin Yim

Young-ju Park

Suhyung Jang

Inoue Naoya

Bongkwan Baek

Sanghyun Lee

Sung Soo Kim

Sungsoo Kim

Kunsik Lee

Hyungjin Kim

Jinyoung Kim

Woojin Lee

Dohyoung Kim

Jang-Hee Lee

Gilheyun Choi

Ik Soo Kim

Sang Hoon Ahn

Junho Shin

Hongsik Shin

Seungwon Ryu

Sunhye Lee

Thomas Oszinda

Jaesung Hur

Tsukasa Matsuda

Euibok Lee

JooHan Kim

Sangkoo Kang

Suhyun Park

Kyungyub Jeon

Gyuhwan Ahn

Hyeoksang Oh

Misuk Park

Junhyuk Lim

Seonghun Lim

Yeonggil Kim

Jongseo Hong

Sungbin Park

Taeksoo Jeon

Yoonhee Kang

A semiconductor device may include PMOSFET and NMOSFET regions spaced apart from each other on a substrate, first and second active patterns provided on the PMOSFET and NMOSFET regions, respectively, a first channel pattern on the first active pattern, a source/drain pattern electrically connected to the first channel pattern, an active contact electrically connected to the source/drain pattern, the active contact including a first conductive pattern and a first barrier pattern enclosing a portion of a side surface and a bottom surface of the first conductive pattern, a gate electrode extending in a direction crossing the first channel pattern, a gate contact electrically connected to the gate electrode, an air gap provided on the first barrier pattern and between the gate contact and the first conductive pattern, and a lower via provided on the active contact. The lower via may be adjacent to the air gap.

Semiconductor device

A semiconductor device including a first conductive layer on a substrate, a second conductive layer on the first conductive layer, a contact structure between the first and second conductive layers, and a barrier structure surrounding a lower region of a side surface of the second conductive layer, wherein the contact structure includes a contact conductive layer having a first upper surface portion and a second upper surface extending from the first upper surface portion and being concave, and a gap-fill pattern fills a space between the second upper surface portion and the second conductive layer and includes a first gap-fill insulating layer including a metal element and a second gap-fill insulating layer including a silicon element, and the barrier structure includes a first etch stop layer and a barrier layer that include same materials as the first insulating material and the second insulating material, respectively, may be provided.

Semiconductor devices

A semiconductor device includes a substrate having an active region, a first insulating layer on the substrate, a second insulating layer on the first insulating layer, an etch stop layer between the first insulating layer and the second insulating layer, a via contact in the first insulating layer and electrically connected to the active region, an interconnection electrode in the second insulating layer and electrically connected to the via contact, a conductive barrier layer on a side surface and a lower surface of the interconnection electrode and having an extension portion extending to a partial region of a side surface of the via contact, and a side insulating layer on a side region of the via contact below the extension portion of the conductive barrier layer, the side insulating layer including the same material as a material of the etch stop layer.

A semiconductor device includes an active region extending on a substrate in a first direction, a gate structure including a gate electrode extending on the substrate in a second direction and traversing the active region, a spacer structure extending on opposing sidewalls of the gate electrode in the second direction, and a capping layer on the gate electrode and the spacer structure, a source/drain region on the active region adjacent the gate structure, and a first contact plug connected to the source/drain region and a second contact plug connected to the gate structure. The capping layer includes a lower capping layer and an upper capping layer on the lower capping layer, and the second contact plug penetrates through the capping layer, is connected to the gate electrode and includes a convex sidewall penetrating into the upper capping layer.

A semiconductor device includes a gate structure disposed on a substrate; a source and drain layer disposed on the substrate adjacent the gate structure; a first contact plug disposed on the source and drain layer, an insulation pattern structure disposed on the first contact plug, the insulation pattern structure including insulation patterns having different carbon concentrations; and a second contact plug disposed on the gate structure.

Semiconductor devices including insulation patterns with different carbon concentrations

A semiconductor device includes active fins extending in a first direction on a substrate; an isolation insulating layer covering a portion of side surfaces of the active fins; channel layers stacked vertically and spaced apart on the active fins; a gate pattern in a second direction across the active fins and the channel layers; and spacer layers across the active fins in the second direction on both sides of the gate pattern. At least one spacer layer extends downwardly along a side surface of the gate pattern such that a lower surface thereof contacts the isolation insulating layer. The lower surface of the spacer layer is higher than a level of upper surfaces of the active fins. The gate pattern has a lower surface contacting the isolation insulating layer. The lower surface of the gate pattern is lower than a level of the upper surfaces of the active fins.

Multi-bridge channel field effect transistor with multiple inner spacers

A sensing device includes a touch panel including first and second sensor electrodes, and a touch panel controller acquiring a sensing signal from the touch panel and detecting a user input based on the sensing signal. The touch panel controller acquires the sensing signal from at least one of the first sensor electrodes and the second sensor electrodes in a first mode operating at a first power. The touch panel controller selects a first transmitting electrode, a second transmitting electrode, and receiving electrodes from one of the first sensor electrodes and the second sensor electrodes, inputs a first driving signal to the first transmitting electrode, and inputs a second driving signal having a phase difference of 180 degrees with respect to the first driving signal to the second transmitting electrode in a second mode operating at a second power and a third mode in which a sensing operation is performed.

Touch panel controller including a sensing circuit configured to drive a touch panel

A semiconductor integrated circuit device includes a substrate; a transistor on the substrate; an interlayer insulating film on the transistor; an insulating liner on the interlayer insulating film; a first insulating film on the insulating liner; and a first wiring layer on the interlayer insulating film and surrounded by the insulating liner. A height of a top surface of the first insulating film in a vertical direction from a main surface of the interlayer insulating film is different than a height of a top surface of the first wiring layer in the vertical direction. A step exists between the top surfaces of the first wiring layer and the first insulating film. A height of the first insulating film is greater than a height of the first wiring layer. A width of the first wiring layer gradually narrows as the first wiring layer extends upwards along the vertical direction.

Semiconductor integrated circuit device suppressing leakage current of multilayer wiring structures

A semiconductor device includes a first active pattern disposed on a substrate, a device isolation layer filling a trench that defines the first active pattern, a first channel pattern and a first source/drain pattern disposed on the first active pattern in which the first channel pattern includes semiconductor patterns stacked and spaced apart from each other, a gate electrode that extends and runs across the first channel pattern, a gate dielectric layer disposed between the first channel pattern and the gate electrode, and a first passivation pattern disposed between the device isolation layer and a first sidewall of the first active pattern. The first passivation pattern includes an upper part that protrudes upwardly from the device isolation layer, and a lower part buried in the device isolation layer. The gate dielectric layer covers the upper part of the first passivation pattern.

Semiconductor device including passivation patterns

A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.

An image sensor includes a semiconductor substrate having a plurality of pixel regions arranged in a first direction and a second direction that are parallel to an upper surface of the semiconductor substrate. The first direction is perpendicular to the second direction. A grid structure extends in the first direction and the second direction on the semiconductor substrate to define openings corresponding to a plurality of sub-pixel regions of the plurality of the pixel regions, respectively. Color filters are disposed in the openings of the grid structure, respectively. A protective layer covers sidewalls of the grid structure and bottom surfaces of the color filters. The protective layer includes silicon oxide including carbon (C) or nitrogen (N).

Image sensor including a protective layer

Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.

Sensing device including a first electrode receiving a first driving signal and a second electrode receiving a second driving signal

A semiconductor device includes a first insulating layer disposed on a substrate, a first wiring disposed in the first insulating layer, a first insulating barrier layer disposed on the first insulating layer, an etch-stop layer disposed on the first insulating barrier layer and having an area smaller than an area of the first insulating barrier layer in a plan view, a resistive metal pattern disposed on the etch-stop layer, a second insulating barrier layer disposed on the resistive metal pattern, a second insulating layer covering the first and second insulating barrier layers, a second wiring disposed in the second insulating layer, and a first conductive via disposed between the resistive metal pattern and the second wiring to penetrate through the second insulating barrier layer and the second insulating layer and electrically connect the resistive metal pattern and the second wiring.

Semiconductor device and method of manufacturing semiconductor device

Growing community of inventors

Suwon-si, South Korea

Jongmin Baek