Samsung Electronics Co., Ltd.

Jongkook Kim

Jangwoo Lee

Kyoungsei Choi

Yoonha Jung

Bona Baek

Jin-Woo Park

Heeseok Lee

Su-Min Park

Min-Ok Na

Hyo-Chang Ryu

Hohyeuk Im

BongJin Son

Jung-Do Lee

Byoungwook Jang

Donghan Kim

Taehoon Kim

Sang-Uk Han

Yunhee Kim

Doohwan Lee

Dongho Lee

Seok Won Lee

Eunseok Cho

SeokWon Lee

Soojeoung Park

Byoung Wook Jang

Hak-Kyoon Byun

Sayoon Kang

JeongHo Lee

Hongwon Kim

Seonmi Lee

Kijae Song

Jaesik Lee

Junmo Koo

Yeonjoo Kim

Hwanggil Shim

Gowoon Seong

Seonhyang You

A semiconductor package includes a base substrate, an interposer package disposed on the base substrate, and first and second semiconductor chips disposed on the interposer package, the interposer package includes a first redistribution layer, a bridge chip including a bridge circuit, and a vertical connection structure including a plurality of wiring layers, and wherein each of the first semiconductor chip and the second semiconductor chip is electrically connected to the bridge circuit and the plurality of wiring layers through the first redistribution layer.

Semiconductor package

A test board for testing a semiconductor apparatus includes a first board configured to support a plurality of first Devices Under Test (DUTs) such that the plurality of first DUTs are mounted on the first board, a plurality of first inter-board connectors arranged on the first board, and a plurality of second boards stacked on the first board through the plurality of first inter-board connectors, each second board of the plurality of second boards having a surface configured to support a separate second DUT of a plurality of second DUTs such that the plurality of second DUTs are mounted on separate, respective second boards of the plurality of second board.

Test board and test apparatus including the same

Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.

Thermal interface material layer and package-on-package device including the same

A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.

Semiconductor packages having semiconductor chips disposed in opening in shielding core plate

Packages substrates are provided. The package substrates may include a substrate and a set of leads disposed on the substrate. The set of lead may include a first lead, a second lead and a third lead, which are sequentially disposed along a first direction. Each of the first lead, the second lead and the third lead may extend along a second direction that is different from the first direction. The first lead and the second lead may be spaced apart at a first distance, and the second lead and the third lead may be spaced apart at a second distance that is less than the first distance.

Package substrates and integrated circuit packages including the same

Package-on-package (POP) devices and methods of manufacturing the POP devices are provided. In the POP devices, a thermal interface material layer disposed between lower and upper semiconductor packages may contact about 70% or greater of an area of a top surface of a lower semiconductor chip. According to methods, the upper semiconductor package may be mounted on the lower semiconductor chip using a weight.

Package-on-package devices and methods of manufacturing the same

Provided is a semiconductor package including a lower package, an interposer on the lower package, and an upper package on the interposer. The lower package may include a lower package substrate, a lower semiconductor chip on the lower package substrate, and a lower heat-transfer layer on the lower semiconductor chip. The interposer may include an interposer substrate, first and second heat-transfer openings defined by recessed bottom and top surfaces, respectively, of the interposer substrate, an upper interposer heat-transfer pad disposed in the second heat-transfer opening, and an upper heat-transfer layer disposed on the upper interposer heat-transfer pad. The upper package may include an upper package substrate, an upper package heat-transfer pad, which may be disposed in a third heat-transfer opening defined by a recessed bottom surface of the upper package substrate, and an upper semiconductor chip disposed on the upper package substrate.

Semiconductor package and method of fabricating the same

Provided are a semiconductor package and a method of fabricating the same. The package substrate includes a hole, which may be used to form a mold layer without any void. The mold layer may be partially removed to expose a lower conductive pattern. Accordingly, it is possible to improve routability of solder balls.

Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer.

Semiconductor chips having guard rings and methods of fabricating the same

Provided is a semiconductor package and a method for fabricating the semiconductor package. The semiconductor package may include a first package having a first semiconductor chip mounted on a first substrate and a second package having a second semiconductor chip mounted on a second substrate, the second substrate being bent to cover a side of the first package to contact the first substrate such that the first and second packages are connected electrically.

Semiconductor package and method for manufacturing the same

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Hwaseong-si, South Korea

Jongkook Kim