Columbia University

Jonghyun Oh

Compute-in-memory (CIM) devices and methods for performing vector-matrix multiplication (VMM) are provided. The disclosed CIM device can include a static random access memory (SRAM) array. The SRAM array can include a plurality of column structures. Each column structure can include eight sub-column structures. Each sub-column structure can include at least one bitcell sharing a pair of a local bitline (LBL) and LBLb that can be connected to a pair of global bitlines (GBL) via switches. Each sub-column comprises at least one NOR gate. An even-numbered bitcell can include a wordline 1 (WL1) for a left access transistors, and an odd-numbered bitcell can include a wordline 2 (WL2) for a right access transistors. Every eight columns (8 columns) can be configured to share a hybrid compressor adder-tree (HCA), followed by a bit-first accumulation (BFA).

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New York, NY, United States of America

Jonghyun Oh